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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Nexperia USA Inc. 74HCT109DB,112

Name: 74HCT109DB,112
Brand: Nexperia USA Inc.
SKU: 74HCT109DB,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74HCT109DB,112

Manufacturer:: Nexperia USA Inc.

Category:: Flip Flops

Package:: 16-SSOP (0.209", 5.30mm Width)

Datasheet:: 74HCT109DB,112.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16SSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74HCT109DB,112 from Nexperia is a dual positive-edge-triggered JK flip-flop with asynchronous set (SD) and reset (RD) inputs, complementary Q/Q̅ outputs per section, TTL-compatible input thresholds (V_IH = 2.0 V min, V_IL = 0.8 V max at V_CC = 5 V), 16-pin SO16 package (SOT109-1), and operation across -40 °C to +125 °C. It enables synchronous state control in digital clock-domain interfaces, bus arbitration logic, and counter enable circuits.

For engineers reviewing the 74HCT109DB,112 datasheet, 74HCT109DB,112 pinout, 74HCT109DB,112 application, or 74HCT109DB,112 equivalent, this device supports precise edge-triggered state capture in mixed-logic systems requiring TTL-level compatibility, low-power CMOS operation, and robust noise immunity - critical for industrial control sequencers and legacy interface bridging.

Technical Context

The 74HCT109DB,112 implements two independent JK flip-flops sharing no internal coupling; each features separate J, K, CP, SD, RD, Q, and Q̅ terminals. Its Schmitt-trigger clock input tolerates slow rise/fall times, while asynchronous SD/RD operate independently of CP and override all synchronous functions when asserted LOW.

State transitions follow the standard JK truth table: toggle on J=K=HIGH, hold on J=K=LOW, set on J=HIGH/K=LOW, and reset on J=LOW/K=HIGH - all conditioned by stable J/K inputs one setup time (t_su = 18 ns min at V_CC = 4.5 V) before the LOW-to-HIGH clock edge.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	4.5 V to 5.5 V - ensures compatibility with standard 5 V TTL and mixed-voltage logic systems without level-shifting.
Propagation Delay (t_pd)	20 ns to 53 ns (V_CC = 4.5 V, C_L = 50 pF) - defines maximum achievable clock frequency (f_max = 27 MHz min) in synchronous state machines.
Input Thresholds	V_IH ≥ 2.0 V, V_IL ≤ 0.8 V - guarantees reliable recognition of standard TTL output levels (e.g., 74LS, 74F) without external biasing.
Asynchronous Response	t_PLH/t_PHL ≤ 39 ns (SD/RD to Q/Q̅, V_CC = 4.5 V) - enables sub-40 ns emergency state override for fault recovery or system initialization.
Power Dissipation	I_CC ≤ 40 μA (static, V_CC = 5.5 V) - supports low-quiescent-current designs in battery-backed or energy-constrained control modules.
Operating Temperature	-40 °C to +125 °C - qualified for under-hood automotive ECUs, industrial PLC I/O modules, and outdoor telecom infrastructure.
ESD Robustness	HBM > 2000 V, CDM > 1000 V - reduces handling sensitivity during manual assembly and field rework in production environments.

Pinout & Package

74HCT109DB,112 uses the SO16 plastic small outline package (SOT109-1), 16-pin, 3.9 mm body width, with gull-wing leads and pin 1 index marker.

Pin/Terminal	Circuit Role	Design Meaning
1, 15 (1RD, 2RD)	Asynchronous Reset Input	Active-LOW signal forcing Q = LOW regardless of clock or J/K state - used for power-on initialization or error recovery.
2, 14 (1J, 2J)	Synchronous Data Input	Controls next-state logic when HIGH/LOW with K; determines toggle/set/reset behavior on next clock edge.
3, 13 (1K, 2K)	Synchronous Data Input	Paired with J to define state transition mode; J=K=1 enables toggle, J=1/K=0 enables set, etc.
4, 12 (1CP, 2CP)	Clock Input	Positive-edge-triggered; Schmitt-trigger input accepts slow-rising clocks (e.g., RC-generated) without metastability risk.
5, 11 (1SD, 2SD)	Asynchronous Set Input	Active-LOW signal forcing Q = HIGH independent of clock - provides immediate state assertion for sequencing control.
6, 10 (1Q, 2Q)	True Output	Complementary to Q̅; drives downstream logic loads up to 4 mA (V_OH ≥ 3.98 V at I_O = −4 mA).
7, 9 (1Q̅, 2Q̅)	Complement Output	Inverted version of Q; eliminates need for external inverters in toggle or feedback configurations.
8	GND	Reference ground plane for all internal circuitry and I/O; must be low-impedance connection to minimize switching noise.
16	V_CC	Primary supply rail (4.5–5.5 V); decoupling capacitor (100 nF) required within 5 mm of pin for stable high-speed operation.

Key Features

Feature	Design Value
TTL-compatible input thresholds	Enables direct interfacing with legacy 74LS/74F families without level shifters or pull-ups - reduces BOM count and layout complexity.
Dual independent JK sections	Allows concurrent control of two state variables (e.g., direction + enable in motor drivers) without cross-talk or shared timing constraints.
Schmitt-trigger clock input	Accepts slow or noisy clock edges (e.g., from microcontroller GPIO or RC oscillators) while maintaining deterministic edge detection.
Asynchronous set/reset with priority	Guarantees immediate state override even during clock glitches or metastable conditions - essential for fail-safe system resets.
Wide temperature range (−40 °C to +125 °C)	Validated for use in engine control units, industrial automation cabinets, and base station RF modules without derating.

Applications

Industrial PLC Sequencer

Digital Bus Arbitration

Use Scenario: Controlling multi-step machine cycles (e.g., conveyor start → fill → seal → eject) with precise step advancement.

IC Role / Device Role: Edge-triggered state register storing current step index; SD/RD used for emergency stop or cycle restart.

Use Value: Guaranteed setup/hold timing (t_su = 18 ns, t_h = 3 ns) ensures deterministic state updates under variable scan-cycle jitter.

Use Scenario: Managing shared data bus access among three microcontrollers in an embedded sensor hub.

IC Role / Device Role: Toggle-mode JK flip-flop implementing round-robin grant logic with priority override via SD/RD.

Use Value: Asynchronous reset (t_PHL ≤ 39 ns) allows immediate bus release during fault detection, preventing lockup.

Legacy Interface Bridging

Configurable Counter Enable

Use Scenario: Adapting TTL-level control signals from aging test equipment into a modern 3.3 V FPGA-based measurement system.

IC Role / Device Role: Level-translating latch synchronizing asynchronous TTL strobes to FPGA clock domain using CP edge alignment.

Use Value: TTL input thresholds eliminate external bias resistors; 5 V tolerant inputs prevent damage from legacy 5 V signal overshoot.

Use Scenario: Enabling/disabling a 4-bit binary counter in a programmable logic controller's timer module.

IC Role / Device Role: D-type configuration (J=K tied) generating synchronized enable pulses synchronized to system clock edge.

Use Value: Complementary Q/Q̅ outputs drive both counter enable and reset paths simultaneously, eliminating race conditions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual JK flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74HCT112D,653	Same SO16 package, but dual JK with negative-edge triggering (CP active on HIGH-to-LOW); identical V_CC, temp, and I/O specs.	Requires inverted clock source or additional inverter; unsuitable where positive-edge alignment is mandatory (e.g., sync to MCU GPIO).	Select only if system clock is naturally falling-edge or inverter resources are available; otherwise, 74HCT109DB,112 ensures direct drop-in compatibility.
SN74HCT109DR	Texas Instruments variant in SOIC-16; identical logic function, pinout, and DC specs, but f_max = 25 MHz (vs. 27 MHz) and t_pd = 22 ns (vs. 20 ns typ) at V_CC = 4.5 V.	Slightly lower speed margin in high-frequency counters; same industrial temp rating (−40 °C to +125 °C) and TTL input compatibility.	Preferred for TI-centric BOMs or where second-source qualification is required; verify timing slack in 25+ MHz designs.

Compared with 74HCT112D,653, the 74HCT109DB,112 avoids clock inversion overhead and guarantees positive-edge synchronization; versus SN74HCT109DR, it delivers tighter propagation delay and higher maximum frequency - critical for timing-critical state machines.

Availability

74HCT109DB,112 is available at Aetrix Electronics and suitable for industrial PLC sequencers, digital bus arbitration logic, and legacy interface bridging requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74HCT109DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components - serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74HCT109DB,112 belongs to Nexperia's 74HCT logic family, engineered specifically for seamless interoperability between TTL and CMOS systems while delivering low static power and robust noise immunity in harsh environments.

FAQ

Can 74HCT109DB,112 operate at 3.3 V supply?

No. The 74HCT109DB,112 is specified only for V_CC = 4.5 V to 5.5 V. Its TTL-compatible input thresholds require minimum 4.5 V to guarantee V_IH ≥ 2.0 V and V_IL ≤ 0.8 V per JEDEC JESD7A. Operation below 4.5 V risks incorrect logic interpretation and is outside guaranteed specifications.

What is the maximum clock frequency for reliable toggle operation?

The maximum guaranteed clock frequency for toggle mode is 27 MHz at V_CC = 4.5 V and T_A = +125 °C (f_max = 27 MHz min). At 25 °C and V_CC = 5 V, typical performance reaches 61 MHz, but design margins must respect the worst-case 27 MHz limit for full temperature and voltage range compliance.

How does the Schmitt-trigger clock input improve system reliability?

The Schmitt-trigger on CP provides hysteresis (typ. 0.4 V at V_CC = 5 V), allowing clean edge detection from slowly rising signals (e.g., RC-filtered microcontroller outputs or mechanical switch debounces) without multiple triggering or metastability - eliminating need for external conditioning circuits.

Are the asynchronous set and reset inputs truly independent of the clock?

Yes. SD and RD are fully asynchronous and active-LOW: asserting either forces immediate Q or Q̅ to defined states (HIGH or LOW) regardless of CP state, J/K values, or clock activity. This behavior is verified down to t_PHL = 39 ns (max) from SD/RD assertion to output change at V_CC = 4.5 V and T_A = +125 °C.

74HCT109DB,112 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74HCT

Package/Case:: 16-SSOP (0.209", 5.30mm Width)

Packaging:: Tube

Product Status:: Obsolete

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 55 MHz

Max Propagation Delay @ V, Max CL:: 35ns @ 4.5V, 50pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 4.5V ~ 5.5V

Current - Quiescent (Iq):: 4 µA

Input Capacitance:: 3.5 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SSOP

74HCT109DB,112 FAQ

1.How can I place an order for 74HCT109DB,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HCT109DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HCT109DB,112 reliable?

The price and inventory of 74HCT109DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT109DB,112 is usually 5 days.

3.What payment methods are accepted for 74HCT109DB,112?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT109DB,112 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HCT109DB,112?

74HCT109DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HCT109DB,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HCT109DB,112?

For technical support, including 74HCT109DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT109DB,112 requirements.

6.How does Aetrix verify that 74HCT109DB,112 is sourced from the original manufacturer or authorized distributors?

All 74HCT109DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT109DB,112 meets industry standards.

7.What is the process for return or replacement of 74HCT109DB,112?

All 74HCT109DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT109DB,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HCT109DB,112 part is unused and in its original packaging.

Return procedure for 74HCT109DB,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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