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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Nexperia USA Inc. 74HCT109PW,118

Name: 74HCT109PW,118
Brand: Nexperia USA Inc.
SKU: 74HCT109PW,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74HCT109PW,118

Manufacturer:: Nexperia USA Inc.

Category:: Flip Flops

Package:: 16-TSSOP (0.173", 4.40mm Width)

Datasheet:: 74HCT109PW,118.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74HCT109PW,118 from Nexperia is a dual positive-edge-triggered JK flip-flop with asynchronous set (SD) and reset (RD) inputs, complementary Q/Q̅ outputs per section, TTL-compatible input thresholds (V_IL = 0.8 V, V_IH = 2.0 V), 4.5–5.5 V supply range, and TSSOP16 package. It enables synchronous state control in digital sequencers, clock dividers, and register files where edge-triggered bistability and level-sensitive preset/clear are required.

For engineers reviewing the 74HCT109PW,118 datasheet, 74HCT109PW,118 pinout, 74HCT109PW,118 application, or 74HCT109PW,118 equivalent, this device serves as a drop-in replacement for legacy 74LS109 in 5 V systems requiring low-power CMOS logic with guaranteed TTL input compatibility, precise setup/hold timing (t_su = 18 ns, t_h = 3 ns @ V_CC = 4.5 V), and industrial temperature operation (−40 °C to +125 °C).

Technical Context

This device implements two independent JK flip-flops sharing no internal coupling-each with dedicated J, K, CP, SD, RD, Q, and Q̅ terminals. Its Schmitt-trigger clock input tolerates slow rise/fall times, while asynchronous SD/RD operate independently of CP and override all synchronous functions when asserted LOW.

The JK architecture supports four distinct modes per clock edge: toggle (J=K=HIGH), set (J=HIGH,K=LOW), reset (J=LOW,K=HIGH), and hold (J=K=LOW). Input clamping diodes allow safe interfacing to voltages exceeding V_CC, and latch-up immunity exceeds 100 mA per JESD78 Class II Level B.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	74HCT - TTL-compatible CMOS, enabling direct interface with 74LS/74F without level shifters
Supply Voltage Range	4.5 V to 5.5 V - ensures stable operation across standard 5 V ±5 % rails
Propagation Delay (t_pd)	20 ns max @ V_CC = 4.5 V, CL = 50 pF - supports reliable 27 MHz operation in synchronous designs
Setup/Hold Time	t_su = 18 ns, t_h = 3 ns @ V_CC = 4.5 V - defines minimum J/K stability window before CP rising edge
Output Drive	±4 mA @ V_CC = 4.5 V - sufficient to drive 10 LS-TTL loads or 20 HCMOS inputs
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive modules and industrial PLC I/O stages
Input Thresholds	V_IH = 2.0 V min, V_IL = 0.8 V max - guarantees noise margin >0.4 V against 5 V TTL logic

Pinout & Package

TSSOP16 package (SOT403-1): plastic thin shrink small outline, 16 leads, 4.4 mm body width, 0.65 mm pitch, exposed pad not present, RoHS-compliant.

Pin/Terminal	Circuit Role	Design Meaning
1, 15 (1RD, 2RD)	Asynchronous reset	Active-LOW; forces Q = LOW regardless of clock or J/K state; overrides all synchronous behavior
2, 14 (1J, 2J)	Synchronous data input	Controls next-state transition on rising CP edge per JK truth table; must be stable t_su before edge
3, 13 (1K, 2K)	Synchronous data input	Paired with J to define toggle/set/reset/hold; complements J function in JK latch behavior
4, 12 (1CP, 2CP)	Clock input	Positive-edge-triggered; Schmitt-triggered for noise immunity; edge sensitivity defined at VM = 1.3 V
5, 11 (1SD, 2SD)	Asynchronous set	Active-LOW; forces Q = HIGH independent of CP; priority over J/K but lower than RD
6, 10 (1Q, 2Q)	True output	Complementary to Q̅; capable of sourcing/sinking 4 mA; fanout = 10 LS-TTL
7, 9 (1Q̅, 2Q̅)	Inverted output	Logic complement of Q; electrically identical drive strength and timing to Q
8	GND	Reference ground plane; decoupling capacitor must be placed within 5 mm of this pin
16	V_CC	+5 V supply rail; requires local 100 nF ceramic bypass capacitor between pins 8 and 16

Key Features

Feature	Design Value
Dual independent JK sections	Enables compact implementation of two-bit counters, shift registers, or state machine registers without inter-chip routing
TTL-compatible input levels	Eliminates need for external level translators when interfacing with legacy 74LS or microcontroller GPIOs operating at 5 V
Asynchronous set/reset with priority hierarchy	SD and RD operate outside clock domain; RD takes precedence over SD, ensuring deterministic power-on reset behavior
Clamped inputs with current-limiting support	Integrated diodes allow safe connection to signals up to V_CC + 0.5 V using series resistors - critical for mixed-voltage board design
Industrial temperature grade	Specified performance across −40 °C to +125 °C enables use in motor drives, power supplies, and base station control logic

Applications

Industrial PLC I/O Modules

Digital Test Equipment Sequencers

Use Scenario: Latching sensor status (e.g., emergency stop, limit switch) in real-time control loops with deterministic response.

IC Role / Device Role / Timing Role: Dual JK flip-flop acts as synchronized input sampler and debounced state register; SD/RD enable hardware-initiated fault clearing.

Use Value: Asynchronous reset ensures immediate recovery from fault conditions without waiting for next clock cycle - reducing worst-case reaction time by up to one system clock period.

Use Scenario: Generating precise stimulus patterns for IC functional testing, including multi-cycle edge-aligned sequences.

IC Role / Device Role / Timing Role: Configured as toggle mode divider (J=K=HIGH) to generate ½-frequency clocks, or as D-type (J=K̅) for pattern storage.

Use Value: Guaranteed t_su/t_h specs and sub-25 ns propagation delay ensure setup compliance at 25 MHz test clock rates without added timing margin.

Legacy System Upgrades

Motor Control Logic

Use Scenario: Replacing obsolete 74LS109 in aging instrumentation while retaining PCB layout and firmware.

IC Role / Device Role / Timing Role: Pin- and function-compatible upgrade delivering same logic behavior with 90 % lower static power and improved noise immunity.

Use Value: Identical pinout and TTL input thresholds eliminate redesign; reduced ICC (4 μA typical) lowers thermal load in dense backplane assemblies.

Use Scenario: Implementing direction/state latches and commutation sequencing in BLDC motor drivers.

IC Role / Device Role / Timing Role: One section holds direction command (Q = DIR), second holds enable state (Q = EN); SD/RD coordinate safe startup/shutdown transitions.

Use Value: Asynchronous set/reset allows coordinated deactivation of power stage before changing direction - preventing shoot-through in half-bridge drivers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual JK flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74HCT109PWR	TI part in TSSOP16; identical V_CC, t_pd, and input thresholds; higher ICC (10 μA typ) and no JESD78 latch-up rating published	Valid for commercial-temp (−40 °C to +85 °C) designs only; lacks +125 °C qualification	Select if TI ecosystem alignment or dual-sourcing is required; verify thermal derating above 85 °C
74HC109PW,118	Nexperia HC variant; wider V_CC (2–6 V) but CMOS-level inputs (V_IH = 3.15 V min @ 4.5 V); incompatible with TTL sources	Applicable in mixed-voltage systems (e.g., 3.3 V control + 5 V peripherals) but requires level translation for 74LS interfaces	Choose only when supply flexibility outweighs interface compatibility; avoid in pure 5 V TTL environments

Compared with SN74HCT109PWR, the 74HCT109PW,118 offers superior high-temperature reliability and lower leakage, while the 74HC109PW,118 trades TTL compatibility for broader voltage operation - making the HCT version optimal for drop-in 5 V upgrades demanding extended temperature support.

Availability

74HCT109PW,118 is available at Aetrix Electronics and suitable for industrial automation controllers, test equipment sequencers, legacy system upgrades, and motor control logic requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74HCT109PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions optimized for reliability and energy efficiency.

The 74HCT109 belongs to Nexperia's industry-standard logic family designed specifically for seamless integration into 5 V systems requiring TTL-compatible inputs, low static power, and robust industrial-grade operation.

FAQ

Can 74HCT109PW,118 operate at 3.3 V?

No. The 74HCT109PW,118 is specified only for 4.5 V to 5.5 V operation. At 3.3 V, input thresholds (V_IH = 2.0 V min) exceed 60 % of V_CC, violating TTL compatibility and risking unreliable HIGH recognition. Use 74HC109PW,118 for 3.3 V systems with CMOS-level inputs.

What is the maximum clock frequency supported?

The maximum clock frequency is 27 MHz at V_CC = 4.5 V and T_A = 25 °C, decreasing to 18 MHz at +125 °C due to propagation delay increase. This is derived from t_pd = 53 ns (max) and t_W = 27 ns (min), requiring ≥70 ns minimum clock period for reliable toggling.

How does the priority between SD and RD work?

When both SD and RD are LOW, the reset function dominates and forces Q = LOW. This priority is hardwired in the silicon and documented in Table 3 ("Undetermined" mode yields Q = Q̅ = HIGH only when both are LOW *and* CP is inactive - but RD assertion alone overrides SD). No external arbitration is needed.

Is there a thermal pad on the TSSOP16 package?

No. The SOT403-1 (TSSOP16) package used for 74HCT109PW,118 has no exposed thermal pad. Thermal dissipation relies on PCB copper area connected to pins 8 (GND) and 16 (V_CC). For continuous operation at +125 °C, maintain ≥200 mm² of 2-oz copper pour tied to both pins via multiple vias.

74HCT109PW,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74HCT

Package/Case:: 16-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 55 MHz

Max Propagation Delay @ V, Max CL:: 35ns @ 6V, 50pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 4.5V ~ 5.5V

Current - Quiescent (Iq):: 4 µA

Input Capacitance:: 3.5 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-TSSOP

74HCT109PW,118 FAQ

1.How can I place an order for 74HCT109PW,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HCT109PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HCT109PW,118 reliable?

The price and inventory of 74HCT109PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT109PW,118 is usually 5 days.

3.What payment methods are accepted for 74HCT109PW,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT109PW,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HCT109PW,118?

74HCT109PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HCT109PW,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HCT109PW,118?

For technical support, including 74HCT109PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT109PW,118 requirements.

6.How does Aetrix verify that 74HCT109PW,118 is sourced from the original manufacturer or authorized distributors?

All 74HCT109PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT109PW,118 meets industry standards.

7.What is the process for return or replacement of 74HCT109PW,118?

All 74HCT109PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT109PW,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HCT109PW,118 part is unused and in its original packaging.

Return procedure for 74HCT109PW,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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