Nexperia USA Inc. 74HCT126D,652
- Part No.:
- 74HCT126D,652
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HCT126D,652.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,337
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Product details
Overview
74HCT126D,652 from Nexperia is a quad 3-state buffer/line driver with TTL-compatible inputs and CMOS outputs, operating from 4.5 V to 5.5 V supply, supporting -40 °C to +125 °C industrial temperature range, with 14-pin SO14 (SOT108-1) package and propagation delay of 14 ns (typ.) at VCC = 4.5 V - used for bidirectional bus interfacing in microcontroller peripheral expansion systems.
For engineers reviewing the 74HCT126D,652 datasheet, 74HCT126D,652 pinout, 74HCT126D,652 application, or 74HCT126D,652 equivalent, key selection criteria include TTL-level input compatibility, 3-state output control timing (enable/disable times ≤ 38 ns), SO14 thermal derating (10.1 mW/K above 100 °C), and guaranteed high-impedance isolation during bus contention.
Technical Context
The 74HCT126D,652 implements four independent non-inverting buffers, each with dedicated active-HIGH output enable (nOE) controlling high-impedance OFF-state. Its TTL-input threshold (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 4.5–5.5 V) ensures direct compatibility with legacy 5 V logic families without level-shifting.
Dynamic behavior is characterized by matched enable/disable delays (ten = tdis = 13–38 ns over temperature), low transition time (tt = 5–18 ns), and power dissipation capacitance CPD = 24 pF - enabling predictable timing closure in synchronous bus architectures with 50 pF load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 4.5 V to 5.5 V - ensures stable operation across standard 5 V ±10 % rails without regulation |
| Input Logic Type | TTL-compatible - accepts standard 5 V logic thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) |
| Propagation Delay (tpd) | 14 ns (typ.) at VCC = 4.5 V, CL = 50 pF - enables ≤ 35 MHz bus clocking with margin |
| Enable/Disable Time (ten/tdis) | 13–38 ns over -40 °C to +125 °C - guarantees deterministic bus turnaround in multiplexed data paths |
| Output Drive Strength | ±6.0 mA at VOH/VOL - sufficient to drive 10 LSTTL loads or 50 pF traces without buffering |
| Power Dissipation Capacitance | CPD = 24 pF - allows accurate dynamic power estimation (PD = CPD × VCC² × fi × N) |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood, industrial control, and power-conversion environments |
Pinout & Package
74HCT126D,652 uses the SO14 (SOT108-1) plastic small outline package: 14-lead, 3.9 mm body width, 1.27 mm lead pitch, with gull-wing leads and pin 1 index marker. Thermal resistance θJA = 70 K/W (JEDEC Std. PCB).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (1OE–4OE) | Active-HIGH output enable per buffer - drives corresponding Y output to high-Z when LOW |
| 2, 5, 9, 12 | nA (1A–4A) | Non-inverting data input - directly interfaces microcontroller GPIO or address/data lines |
| 3, 6, 8, 11 | nY (1Y–4Y) | 3-state buffered output - provides isolated, driven signal to shared bus or peripheral interface |
| 7 | GND | Ground reference - must be low-inductance connection to minimize switching noise coupling |
| 14 | VCC | Positive supply - requires local 100 nF ceramic decoupling within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible input thresholds | VIH = 2.0 V min, VIL = 0.8 V max at 4.5–5.5 V - eliminates need for external level shifters with legacy 5 V controllers |
| High-noise-immunity CMOS outputs | VOH ≥ 3.98 V, VOL ≤ 0.26 V at IO = ±6 mA - ensures >1.2 V noise margin in noisy industrial environments |
| Clamp diode-equipped inputs | Enables safe interface to voltages up to VCC + 0.5 V using current-limiting resistors - protects against overvoltage transients |
| ESD robustness | HBM > 2000 V, CDM > 1000 V - reduces field failure risk during handling and board assembly |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level B - prevents destructive latch-up during supply sequencing or fault conditions |
Applications
| Microcontroller Bus Expansion | Industrial I/O Multiplexing |
|---|---|
Use Scenario: Expanding GPIO count of an ARM Cortex-M4 MCU to drive 16-bit parallel LCD and SD card interface on shared data lines. IC Role / Device Role / Timing Role: Bidirectional 3-state buffer isolating MCU data bus from peripherals during arbitration; enables time-multiplexed access with <38 ns enable/disable latency. Use Value: Eliminates need for discrete MOSFET switches or complex CPLD logic, reducing BOM cost and PCB area while maintaining deterministic bus turnaround. |
Use Scenario: Routing analog sensor readings and digital status signals from multiple PLC modules onto a common backplane data bus. IC Role / Device Role / Timing Role: Unidirectional line driver with TTL input compatibility, providing noise-resistant signal integrity across 20 cm ribbon cable runs. Use Value: Delivers ±6 mA drive into 50 pF + 1 kΩ loads, ensuring clean edges at 10 MHz update rates without waveform degradation. |
| Legacy System Interface Adapter | Test Equipment Signal Conditioning |
Use Scenario: Interfacing modern FPGA-based test controller to vintage 1980s instrumentation with 5 V TTL data buses. IC Role / Device Role / Timing Role: Level-translating buffer with TTL input recognition and CMOS output drive, synchronizing to 5 MHz system clock. Use Value: Matches VIH/VIL of 74LS series while sourcing/sinking 3× more current than LS devices - improves setup/hold margins and reduces bit errors. |
Use Scenario: Isolating DUT signal paths in automated test equipment to prevent cross-talk between stimulus and measurement channels. IC Role / Device Role / Timing Role: 3-state gate controlled by test sequencer, enabling channel-by-channel signal routing without loading inactive paths. Use Value: Achieves <1 μA OFF-state leakage (IOZ ≤ ±5 μA), minimizing crosstalk-induced measurement drift in µV-range analog measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT125DR | Same logic function and pinout; TI part with identical VCC range (4.5–5.5 V), but higher ICC (max 160 μA vs. 80 μA at 25 °C) | Higher static current may impact battery-powered designs; otherwise drop-in replacement in fixed-supply systems | Select when TI ecosystem alignment or dual-sourcing is required; verify thermal budget with higher ICC |
| 74LVC126APW,118 | Lower VCC range (1.65–5.5 V); 3.3 V optimized; faster tpd (3.4 ns typ. at 3.3 V), but TTL input thresholds not supported | Requires level translation for 5 V TTL sources; unsuitable for mixed-voltage legacy interfaces | Prefer for new 3.3 V-only designs needing speed/power trade-off; avoid where 5 V TTL compatibility is mandatory |
Compared with SN74HCT125DR and 74LVC126APW,118, the 74HCT126D,652 uniquely balances TTL input compatibility, industrial temperature support, and SO14 thermal performance - making it optimal for retrofitting legacy 5 V systems without redesigning voltage domains or layout.
Availability
74HCT126D,652 is available at Aetrix Electronics and suitable for microcontroller bus expansion, industrial I/O multiplexing, legacy system interface adaptation, and test equipment signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74HCT126D,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on efficiency, reliability, and sustainability - headquartered in Nijmegen, Netherlands.
The 74HCT126D,652 belongs to Nexperia's industry-standard 74HCT logic family, engineered specifically for robust 5 V TTL-to-CMOS interfacing in automotive-adjacent industrial and computing applications.
FAQ
Can 74HCT126D,652 operate at 3.3 V supply?
No. The 74HCT126D,652 is specified only for 4.5 V to 5.5 V operation per its recommended conditions table. At 3.3 V, TTL input thresholds (VIH ≥ 2.0 V) cannot be reliably met, and output drive strength degrades significantly - use 74LVC126 for 3.3 V systems instead.
What is the maximum capacitive load this device can drive while maintaining timing specs?
The 74HCT126D,652 is characterized up to 50 pF load (CL = 50 pF) in its dynamic specifications. Driving >50 pF increases propagation delay nonlinearly and may violate setup/hold windows; for >100 pF loads, add series termination or buffer staging per Nexperia Application Note AN10697.
How does the input clamp diode affect external resistor sizing for overvoltage protection?
When interfacing to voltages exceeding VCC, a current-limiting resistor must restrict IVI to ≤ ±20 mA (absolute max). For a 12 V input and VCC = 5 V, minimum resistor is (12 V − 5.5 V)/20 mA = 325 Ω - verified using the clamp diode forward voltage (~0.5 V) and datasheet limiting values table.
Is the SO14 package RoHS-compliant and lead-free?
Yes. The 74HCT126D,652 in SOT108-1 package meets RoHS Directive 2011/65/EU and is lead-free with matte tin (Sn) termination - confirmed in Nexperia's compliance documentation (DocID: QG-000012 rev. 2025-07).
74HCT126D,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HCT
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74HCT126D,652 FAQ
1.How can I place an order for 74HCT126D,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT126D,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT126D,652 reliable?
The price and inventory of 74HCT126D,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT126D,652 is usually 5 days.
3.What payment methods are accepted for 74HCT126D,652?
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74HCT126D,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT126D,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT126D,652?
For technical support, including 74HCT126D,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT126D,652 requirements.
6.How does Aetrix verify that 74HCT126D,652 is sourced from the original manufacturer or authorized distributors?
All 74HCT126D,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT126D,652 meets industry standards.
7.What is the process for return or replacement of 74HCT126D,652?
All 74HCT126D,652 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT126D,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT126D,652 part is unused and in its original packaging.
Return procedure for 74HCT126D,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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