Nexperia USA Inc. 74HCT126PW,118
- Part No.:
- 74HCT126PW,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74HCT126PW,118.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74HCT126PW,118 from Nexperia is a quad 3-state buffer/line driver with TTL-compatible inputs and CMOS outputs, operating from 4.5 V to 5.5 V, delivering 6 mA output drive at VCC = 4.5 V, with propagation delay of 14 ns (typ.) and disable time of 18 ns (typ.) at 4.5 V - used in bus interface isolation and address/data line buffering in industrial microcontroller systems.
For engineers reviewing the 74HCT126PW,118 datasheet, 74HCT126PW,118 pinout, 74HCT126PW,118 application, or 74HCT126PW,118 equivalent, key selection criteria include TTL-level input compatibility, 3-state enable timing (tdis, ten), thermal derating above +81 °C for TSSOP14, and IOZ leakage under high-impedance conditions.
Technical Context
This device implements four independent non-inverting buffers, each with active-HIGH output enable (1OE–4OE) controlling high-impedance (Z) state on corresponding outputs (1Y–4Y). Input clamping diodes allow safe interfacing to voltages exceeding VCC when current-limiting resistors are used.
It operates across -40 °C to +125 °C, supports dynamic power calculation via CPD = 24 pF, and meets JEDEC JESD7A (2.0–6.0 V) and JESD8C (2.7–3.6 V) standards - though 74HCT126 variant is specified only for 4.5–5.5 V operation per its recommended conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - defines valid rail range for TTL-compatible input thresholds and guaranteed output swing. |
| Input Voltage Levels | VIL ≤ 0.8 V, VIH ≥ 2.0 V - ensures direct compatibility with standard 5 V TTL logic families without level shifting. |
| Output Drive | ±6.0 mA at VCC = 4.5 V - sufficient to drive 50 pF loads with <30 ns propagation delay in typical bus applications. |
| Propagation Delay | 14 ns (typ.) nA→nY at VCC = 4.5 V, CL = 50 pF - determines maximum data rate in synchronous bus environments. |
| Disable Time | 18 ns (typ.) nOE→nY at VCC = 4.5 V - critical for bus turnaround timing in bidirectional data transfer protocols. |
| Off-State Leakage | ±5.0 μA max at VCC = 5.5 V - ensures minimal current draw and signal integrity during 3-state hold. |
| Operating Temperature | -40 °C to +125 °C - validated for extended industrial and automotive-adjacent control unit deployments. |
Pinout & Package
TSSOP14 plastic thin shrink small outline package (SOT402-1), 14-lead, body width 4.4 mm, 0.65 mm pitch, 1.20 mm max height - optimized for high-density PCB layouts with improved thermal dissipation over SO14.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | 1OE, 2OE, 3OE, 4OE | Active-HIGH output enable inputs - assert HIGH to activate corresponding buffer output (nY); LOW forces high-impedance state. |
| 2, 5, 9, 12 | 1A, 2A, 3A, 4A | Buffer input terminals - accept TTL-level signals and drive respective outputs with non-inverting logic. |
| 3, 6, 8, 11 | 1Y, 2Y, 3Y, 4Y | Buffer output terminals - deliver CMOS-level outputs with 3-state capability controlled by OE pins. |
| 7 | GND | Ground reference (0 V) - return path for all internal logic and output currents; must be low-impedance. |
| 14 | VCC | Positive supply rail - powers all four buffers and enables specified DC and switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible inputs | VIH ≥ 2.0 V, VIL ≤ 0.8 V at VCC = 4.5–5.5 V - eliminates need for external level translators when interfacing legacy 5 V TTL systems. |
| CMOS output drive | VOH ≥ 3.98 V, VOL ≤ 0.26 V at IO = ±6 mA - ensures robust noise margin and fanout capability into standard CMOS loads. |
| Input clamp diodes | Integrated ESD protection diodes to VCC and GND - allows safe connection of inputs to voltages > VCC when series resistors limit current to <20 mA. |
| High-impedance control | IOZ ≤ ±5.0 μA at VCC = 5.5 V - minimizes bus contention current and leakage during tri-state operation in shared-bus architectures. |
| Wide temperature range | Specified from -40 °C to +125 °C - supports deployment in industrial motor drives, PLC I/O modules, and power supply monitoring circuits. |
Applications
| Industrial Bus Isolation | Microcontroller GPIO Expansion |
|---|---|
|
Use Scenario: Isolating multiple microcontroller address/data buses sharing a common memory or peripheral bus. IC Role / Device Role / Timing Role: Quad 3-state buffer enabling time-multiplexed access by asserting OE lines to selectively connect one controller's bus while others remain high-Z. Use Value: Prevents bus contention during multi-master arbitration; 18 ns disable time ensures clean bus release before next master asserts. |
Use Scenario: Expanding limited GPIO count of an MCU to drive multiple LED indicators, relay drivers, or sensor enable lines. IC Role / Device Role / Timing Role: Level-shifting and current-boosting buffer between MCU I/O pins and higher-current external loads. Use Value: Delivers 6 mA per output - sufficient to directly drive LEDs or small logic inputs without discrete transistors. |
| Legacy System Interface | Test Equipment Signal Conditioning |
|
Use Scenario: Interfacing modern 3.3 V or 5 V microcontrollers to legacy TTL-based instrumentation or control panels. IC Role / Device Role / Timing Role: Translating TTL logic levels to CMOS-compatible outputs while maintaining timing integrity. Use Value: Guaranteed VIH/VIL thresholds match standard TTL families, eliminating false triggering in noisy factory-floor environments. |
Use Scenario: Conditioning digital stimulus/response signals in automated test equipment (ATE) where signal integrity and channel isolation are critical. IC Role / Device Role / Timing Role: Buffering and gating test vectors using OE control to prevent back-driving of DUT pins during measurement phases. Use Value: Low off-state leakage (<5 μA) avoids loading sensitive analog measurement nodes during high-Z periods. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT125DR | Same function, but uses active-LOW OE (nOE); 14-pin SOIC (SO14) package; slightly higher tdis (20 ns typ.) | Requires inverted OE control logic; less suitable for space-constrained designs due to larger SOIC footprint | Select if existing PCB layout uses SOIC or system logic naturally provides active-LOW enable signals. |
| 74LVC126APW | Lower VCC range (1.65–5.5 V); LVTTL-compatible inputs; 32 mA drive; smaller 1.2 mm height TSSOP14 | Better suited for mixed-voltage systems (e.g., 1.8 V/3.3 V/5 V domains); higher drive may require series termination | Choose for future-proofing in multi-rail designs or where higher output current is required beyond 6 mA. |
Compared with SN74HCT125DR and 74LVC126APW, the 74HCT126PW,118 offers optimal balance of TTL compatibility, compact TSSOP14 packaging, and precise 18 ns disable timing - making it preferred for retrofitting legacy 5 V bus interfaces where OE polarity and package size are fixed constraints.
Availability
74HCT126PW,118 is available at Aetrix Electronics and suitable for industrial bus isolation, microcontroller GPIO expansion, legacy system interface, and test equipment signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74HCT126PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential semiconductors - delivering high-performance, reliable components for automotive, industrial, mobile, and consumer applications.
The 74HCT126 belongs to Nexperia's 74HCT logic family, engineered for seamless integration between TTL and CMOS systems in industrial control and embedded interface applications.
FAQ
Can 74HCT126PW,118 operate at 3.3 V supply?
No. The 74HCT126 variant is specified only for 4.5 V to 5.5 V operation per its recommended conditions. At 3.3 V, input thresholds (VIH ≥ 2.0 V) may still be met, but VOH/VOL, timing, and drive strength are not guaranteed - use 74LVC126 or 74AHCT126 for 3.3 V compatibility.
What is the thermal derating behavior for TSSOP14 package?
The TSSOP14 (SOT402-1) package derates total power dissipation linearly at 7.3 mW/K above +81 °C. At +125 °C ambient, Ptot reduces from 500 mW to approximately 468 mW - requiring attention to board copper area and airflow in high-temperature enclosures.
How does input clamping affect interfacing with 12 V signals?
Clamp diodes allow safe connection of inputs to voltages up to VCC + 0.5 V, but for 12 V signals, a series current-limiting resistor must restrict IIK to ≤ ±20 mA. At VCC = 5 V, minimum R = (12 V − 5.5 V)/20 mA = 325 Ω - verified in Section 7 limiting values.
Is there a pin-compatible 74HCT126 variant with different enable polarity?
No. All 74HCT126 variants (including PW, D, DB packages) use active-HIGH OE inputs. For active-LOW enable, the functionally equivalent part is 74HCT125 - which shares identical pinout except OE pins are inverted in logic function and labeled nOE.
74HCT126PW,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HCT
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
74HCT126PW,118 FAQ
1.How can I place an order for 74HCT126PW,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT126PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT126PW,118 reliable?
The price and inventory of 74HCT126PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT126PW,118 is usually 5 days.
3.What payment methods are accepted for 74HCT126PW,118?
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74HCT126PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT126PW,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT126PW,118?
For technical support, including 74HCT126PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT126PW,118 requirements.
6.How does Aetrix verify that 74HCT126PW,118 is sourced from the original manufacturer or authorized distributors?
All 74HCT126PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT126PW,118 meets industry standards.
7.What is the process for return or replacement of 74HCT126PW,118?
All 74HCT126PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT126PW,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT126PW,118 part is unused and in its original packaging.
Return procedure for 74HCT126PW,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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