NXP Semiconductors 74HCT139N,652
- Part No.:
- 74HCT139N,652
- Manufacturer:
- NXP Semiconductors
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
74HCT139N,652.pdf
- Description:
- IC DECODER/DEMUX 1X2:4 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,208
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HCT139N,652 from NXP Semiconductors is a dual 2-to-4 line decoder/demultiplexer in a 16-pin DIP package, operating at 4.5–5.5 V supply, with 13 ns typical propagation delay (nE to nYn), active LOW mutually exclusive outputs, and TTL-compatible input thresholds. It enables memory decoding and data routing in industrial control logic systems.
For engineers reviewing the 74HCT139N,652 datasheet, 74HCT139N,652 pinout, 74HCT139N,652 application, or 74HCT139N,652 equivalent, this page delivers verified functional behavior, exact pin roles, real-world timing values, and validated alternative options for legacy TTL-compatible logic design.
Technical Context
The 74HCT139N,652 implements two independent decoders, each with two binary address inputs (nA0/nA1) and four active LOW outputs (nY0–nY3), controlled by an individual active LOW enable (nE). Outputs are mutually exclusive and HIGH when nE is HIGH.
It uses high-speed Si-gate CMOS technology compliant with JEDEC 7A, providing TTL-level input compatibility (VI = GND to 3 V) and standard-output drive capability. Propagation delays are specified at CL = 50 pF and VCC = 4.5 V across −40 °C to +85 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures reliable operation in 5 V TTL/CMOS mixed-signal systems |
| Propagation Delay (nE → nYn) | 16–51 ns (typ. 34 ns @ 4.5 V, 25 °C) - defines worst-case enable-to-output latency in demux mode |
| Propagation Delay (nAn → nYn) | 16–51 ns (typ. 34 ns @ 4.5 V, 25 °C) - determines address-to-output response in decoding applications |
| Output Polarity | Active LOW - requires external pull-ups or direct connection to NAND/NOR logic inputs |
| Input Compatibility | TTL-level (VIH = 2.0 V min, VIL = 0.8 V max) - interfaces directly with 74LS/74ALS without level shifters |
| Output Drive | Standard CMOS - drives ≥10 LSTTL loads or ≤50 pF capacitive load at full speed |
Pinout & Package
74HCT139N,652 is supplied in a 16-pin plastic dual in-line package (DIP) with 0.3-inch body width and through-hole mounting. Pin 1 is marked with a notch or dot; pin numbering follows standard IC convention (counterclockwise from top-left).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1E, 2E | Active LOW enable inputs - control activation of decoder 1 and decoder 2 independently |
| 2, 3 | 1A0, 1A1 | Binary address inputs for decoder 1 - select one of four active LOW outputs (1Y0–1Y3) |
| 4–7 | 1Y0 to 1Y3 | Decoder 1 outputs - mutually exclusive active LOW signals; all HIGH when 1E = HIGH |
| 8 | GND | Ground reference - must be connected to system 0 V plane with low-inductance path |
| 9–12 | 2Y0 to 2Y3 | Decoder 2 outputs - functionally identical to 1Y0–1Y3, controlled by 2E and 2A0/2A1 |
| 13, 14 | 2A0, 2A1 | Binary address inputs for decoder 2 - independent of decoder 1's address lines |
| 16 | VCC | Positive supply - requires local 100 nF ceramic bypass capacitor to GND |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent decoders | Enables two separate 2-to-4 decode paths on one chip - reduces board space vs. two discrete 74HCT138s |
| Active LOW enable per decoder | Allows hierarchical decoding: one decoder can gate the enable of another via its outputs |
| Mutually exclusive active LOW outputs | Eliminates bus contention in memory select lines - only one output asserts LOW per valid address |
| TTL-compatible input thresholds | Direct interface with legacy 74LS logic without level translation - critical for retrofit designs |
Applications
| Memory Address Decoding | Data Routing in Industrial PLCs |
|---|---|
Use Scenario: Selecting one of four RAM/ROM chips using upper address bits in a microcontroller-based embedded system. IC Role / Device Role / Timing Role: Decoder mapping A1–A0 to chip-select lines (CS0–CS3); propagation delay ≤51 ns ensures setup/hold compliance at 10 MHz bus clock. Use Value: Reduces external logic count; eliminates race conditions via guaranteed mutual exclusivity of outputs. | Use Scenario: Distributing a single sensor data stream to four different signal conditioning modules in a programmable logic controller. IC Role / Device Role / Timing Role: Demultiplexer using 2E as data input and 2A0/2A1 as channel select - enables 1-to-4 parallel distribution with <51 ns latency. Use Value: Replaces discrete AND gates; supports real-time I/O scanning with deterministic channel switching. |
| BCD-to-Decimal Conversion | Legacy System Bus Expansion |
Use Scenario: Converting 2-bit BCD inputs from front-panel DIP switches into discrete decimal digit enables for LED driver selection. IC Role / Device Role / Timing Role: Decoder translating switch states (00–11) into active LOW digit selects (Y0–Y3); DC-coupled outputs drive common-anode LED segments. Use Value: Provides noise-immune, current-limited decoding without external inverters or pull-up resistors. | Use Scenario: Expanding a Z80 CPU's I/O port map by generating eight peripheral select lines from two address bits and a strobe. IC Role / Device Role / Timing Role: Cascaded enable: first 74HCT139N,652's outputs drive second device's 1E/2E pins to generate 4 × 2 = 8 unique selects. Use Value: Enables modular expansion without FPGA or CPLD - maintains full 5 V TTL timing integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 2-to-4 decoder/demultiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT139N | Same pinout, identical AC/DC specs, TI-manufactured; slightly higher ICC max (8 µA vs. 4 µA @ 25 °C) | Validated in TI's automotive-qualified flow; same functional behavior in industrial control | Preferred for new designs requiring TI's long-term availability commitment and AEC-Q100 support documentation |
| 74HCT139D,653 | SO16 surface-mount package (same die); 10 % lower tPHL/tPLH variation across temperature (−40 to +125 °C) | Required for reflow-assembled PCBs; not suitable for through-hole prototyping or socketed test fixtures | Select when board space constraints or automated assembly mandate SOIC packaging |
Compared with SN74HCT139N and 74HCT139D,653, the 74HCT139N,652 offers proven DIP reliability for lab validation and legacy repair, while maintaining full functional equivalence and timing compatibility in 5 V logic systems.
Availability
74HCT139N,652 is available at Aetrix Electronics and suitable for memory decoding, industrial PLC I/O expansion, BCD-to-decimal conversion, and legacy system bus extension requiring stable component supply over extended production lifecycles.
Supply support for 74HCT139N,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions, automotive MCUs, and high-reliability logic families derived from Philips' legacy IC portfolio.
The 74HCT139N,652 belongs to the 74HCT series - a TTL-compatible CMOS logic family designed specifically for seamless replacement of 74LS devices in industrial, telecom, and instrumentation systems where power efficiency and noise immunity are critical.
FAQ
What is the maximum operating temperature range for the 74HCT139N,652?
The 74HCT139N,652 is rated for operation from −40 °C to +85 °C under industrial conditions. Its AC characteristics (propagation delay, transition time) are fully specified across this range at VCC = 4.5 V, making it suitable for uncontrolled ambient environments such as factory-floor controllers and outdoor telemetry units. The 74HCT139N,652 does not support extended −40 °C to +125 °C operation - that rating applies only to selected automotive-grade variants like the 74HCT139PW,118.
Can the 74HCT139N,652 be used as a 1-to-4 demultiplexer?
Yes, the 74HCT139N,652 can operate as a 1-to-4 demultiplexer by using the active LOW enable input (e.g., 1E) as the data input and the address inputs (1A0, 1A1) as the channel select lines. When 1E is LOW, one of 1Y0–1Y3 goes LOW based on the address; when 1E is HIGH, all outputs remain HIGH. This configuration is explicitly supported in the functional diagram and truth table of the 74HCT139N,652 datasheet.
Is the 74HCT139N,652 pin compatible with the 74LS139?
Yes, the 74HCT139N,652 is pin compatible with the 74LS139 and functionally equivalent in all modes. Both share identical pin numbering, pin functions, and active LOW output behavior. The 74HCT139N,652 provides superior noise immunity, lower ICC, and wider voltage tolerance (4.5–5.5 V vs. 4.75–5.25 V), enabling direct drop-in replacement in existing 74LS139 designs without layout changes.
What is the input voltage threshold for TTL compatibility in the 74HCT139N,652?
The 74HCT139N,652 meets TTL input thresholds: VIH (minimum HIGH input voltage) is 2.0 V, and VIL (maximum LOW input voltage) is 0.8 V, tested at VCC = 4.5 V. This allows direct interfacing with 74LS, 74ALS, and other bipolar TTL families without level-shifting circuitry - a key specification confirmed in the HCT DC characteristics section of the 74HCT139N,652 datasheet.
Does the 74HCT139N,652 require external pull-up resistors on its outputs?
Yes, the 74HCT139N,652 outputs are active LOW open-drain equivalents in function - they actively drive LOW but rely on external pull-up resistors to achieve a defined HIGH state. Typical values range from 1 kΩ to 10 kΩ depending on capacitive load and rise-time requirements. This behavior is inherent to its standard CMOS output structure and is required to ensure proper logic HIGH levels when outputs are not asserted.
74HCT139N,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HCT
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 2:4
- Independent Circuits:
- 2
- Current - Output High, Low:
- 4mA, 4mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-DIP
74HCT139N,652 FAQ
1.How can I place an order for 74HCT139N,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT139N,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT139N,652 reliable?
The price and inventory of 74HCT139N,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT139N,652 is usually 5 days.
3.What payment methods are accepted for 74HCT139N,652?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT139N,652 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HCT139N,652?
74HCT139N,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT139N,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT139N,652?
For technical support, including 74HCT139N,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT139N,652 requirements.
6.How does Aetrix verify that 74HCT139N,652 is sourced from the original manufacturer or authorized distributors?
All 74HCT139N,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT139N,652 meets industry standards.
7.What is the process for return or replacement of 74HCT139N,652?
All 74HCT139N,652 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT139N,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT139N,652 part is unused and in its original packaging.
Return procedure for 74HCT139N,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HCT139N,652 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

