Nexperia USA Inc. 74HCT1G126GW,125
- Part No.:
- 74HCT1G126GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74HCT1G126GW,125.pdf
- Description:
- IC BUF NON-INVERT 5.5V 5TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:29,678
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Product details
Overview
74HCT1G126GW,125 from Nexperia is a single 3-state bus buffer/line driver with TTL-compatible inputs, 5-pin TSSOP package, VCC range 4.5–5.5 V, propagation delay ≤30 ns at 4.5 V, and operation up to +125 °C. It enables bidirectional data isolation in compact digital interfaces such as I²C level-shifting bridges and microcontroller GPIO expanders.
For engineers reviewing the 74HCT1G126GW,125 datasheet, 74HCT1G126GW,125 pinout, 74HCT1G126GW,125 application, or 74HCT1G126GW,125 equivalent, this device is selected for low-power, high-noise-immunity signal buffering where precise enable-controlled output impedance and guaranteed TTL input thresholds are required in space-constrained industrial control modules.
Technical Context
The 74HCT1G126GW,125 implements a single non-inverting buffer with active-low 3-state output control (OE), supporting true bus-hold-free tri-state operation. Its TTL-level input thresholds (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 5 V) ensure compatibility with legacy 5 V logic families without level translation.
It features symmetrical output drive capability (±6 mA at VCC = 4.5 V), balanced propagation delays (tpd = ten = tdis ≈ 10–36 ns), and integrated input clamp diodes enabling safe interfacing to voltages exceeding VCC when used with current-limiting resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - Ensures stable operation across standard 5 V supply rails with ±10 % tolerance. |
| Input Thresholds | VIH = 2.0 V min, VIL = 0.8 V max - Guarantees reliable recognition of TTL logic levels without external biasing. |
| Output Drive | ±6.0 mA at VCC = 4.5 V - Supports direct connection to 50 pF loads and multiple CMOS inputs without fanout limitation. |
| Propagation Delay | 11 ns typ (A→Y), 30 ns max at VCC = 4.5 V - Enables use in sub-30 MHz synchronous data paths with deterministic timing. |
| Enable/Disable Time | ten = 35 ns max, tdis = 38 ns max at VCC = 4.5 V - Allows clean bus arbitration in shared-data applications like SPI peripheral multiplexing. |
| Operating Temp | −40 °C to +125 °C - Qualified for under-hood automotive ECUs and industrial motor drives without derating. |
| ESD Rating | HBM >2000 V, CDM >1000 V - Reduces need for external protection in handheld test equipment and field-deployed sensors. |
Pinout & Package
TSSOP5 (SOT353-1) plastic thin shrink small outline package, 5-lead, body width 1.25 mm, 0.65 mm pitch, lead-to-lead width 2.2 mm, height 0.95 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output enable input | Active-HIGH control: Y = A when OE = HIGH; Y = high-impedance when OE = LOW. |
| 2 (A) | Data input | Non-inverting input node with clamp diodes - permits overvoltage-safe interface using series resistors. |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output stages; must be low-inductance connection for noise immunity. |
| 4 (Y) | Data output | 3-state buffered output with symmetrical sourcing/sinking; no internal pull-up/down. |
| 5 (VCC) | Supply voltage | Primary power rail; decoupling capacitor (100 nF) required within 5 mm for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible inputs | VIH/VIL thresholds match 5 V TTL families - eliminates need for level shifters in mixed-voltage MCU systems. |
| Clamp diode protected inputs | Enables robust interfacing to signals up to VCC + 0.5 V using simple series resistors - reduces BOM count in sensor front-ends. |
| Symmetrical output impedance | Matched rise/fall times and drive strength - prevents signal distortion on shared buses with capacitive loading. |
| High noise immunity | Typical 400 mV noise margin at VCC = 5 V - sustains reliable operation in electrically noisy PLC backplanes. |
| Latch-up immunity | JESD78 Class II Level B (>100 mA) - ensures survivability during transient overcurrent events in motor-control IO modules. |
Applications
| Industrial Sensor Interface | I²C Bus Isolation |
|---|---|
|
Use Scenario: Connecting analog sensor outputs to a microcontroller ADC input while isolating the sensor ground from noisy digital power domains. IC Role / Device Role / Timing Role: Unidirectional buffer with 3-state control enables ground separation and prevents return-current coupling during ADC sampling windows. Use Value: Eliminates 60 Hz hum and switching noise in precision 12-bit sensor readings without optocouplers or isolated DC/DC. |
Use Scenario: Multiplexing two I²C peripherals onto a single controller bus using software-selectable enable lines. IC Role / Device Role / Timing Role: Bidirectional bus buffer with fast enable/disable (≤38 ns) allows dynamic reconfiguration without clock stretching or bus contention. Use Value: Enables hot-plug capability for modular sensor nodes while maintaining I²C timing compliance (tBUF ≥ 5 μs). |
| Microcontroller GPIO Expansion | Legacy System Glue Logic |
|
Use Scenario: Extending limited GPIO count on an ARM Cortex-M0+ MCU to drive eight discrete indicators via serial-to-parallel shift register feedback. IC Role / Device Role / Timing Role: Output-enable controlled buffer isolates shift register output from MCU pins during configuration writes. Use Value: Prevents spurious LED activation during firmware boot sequences by holding outputs in high-Z until initialization completes. |
Use Scenario: Interfacing a 5 V TTL UART transmitter to a 3.3 V FPGA receiver in a retro-computing restoration project. IC Role / Device Role / Timing Role: Level-tolerant buffer with TTL input thresholds accepts 5 V logic swings and drives 3.3 V CMOS inputs safely. Use Value: Avoids timing skew and voltage translation errors that occur with resistor-divider or MOSFET-based solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G126GV,125 | CMOS input thresholds (VIH = 0.7×VCC), 1.65–5.5 V supply, lower ICC (max 10 μA) | Better suited for battery-powered IoT nodes; not TTL-compatible - requires level matching if driving legacy 5 V logic. | Select when system uses only 1.8/3.3 V logic and ultra-low static power is critical. |
| SN74LVC1G125DBVR | Active-low enable (OE̅), same VCC range and drive strength, TI packaging (SOT-23-5) | Requires inverted enable logic; pinout differs (OE̅ on pin 1 vs OE on pin 1), not drop-in replaceable. | Select only when board layout accommodates SOT-23 footprint and firmware supports active-low enable signaling. |
Compared with 74LVC1G126GV,125 and SN74LVC1G125DBVR, the 74HCT1G126GW,125 uniquely delivers TTL input compatibility at 5 V with industry-standard TSSOP5 pinout and guaranteed +125 °C operation - making it the preferred choice for industrial control retrofit and mixed-voltage legacy interface designs.
Availability
74HCT1G126GW,125 is available at Aetrix Electronics and suitable for industrial automation controllers, automotive body electronics modules, and medical diagnostic instrument signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74HCT1G126GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions with focus on efficiency, miniaturization, and robustness for industrial and automotive markets.
The 74HCT1G126GW,125 belongs to Nexperia's 74HCT logic family, engineered specifically for seamless integration between TTL and CMOS systems in harsh-environment applications demanding wide temperature operation and high ESD resilience.
FAQ
What is the maximum capacitive load the 74HCT1G126GW,125 can drive while maintaining specified timing?
The device is characterized with CL = 50 pF in its dynamic specifications, and typical propagation delay remains within 30 ns max up to this load. Driving >50 pF increases tpd and tdis nonlinearly; for 100 pF loads, measured tpd exceeds 45 ns at VCC = 4.5 V. Use series termination or buffer staging for heavier loads.
Can the 74HCT1G126GW,125 be used with a 3.3 V supply?
No - the 74HCT variant is specified only for VCC = 4.5–5.5 V per JEDEC JESD8C. At 3.3 V, VIH minimum (2.0 V) exceeds 60 % of VCC, violating TTL threshold definitions and risking unreliable HIGH detection. Use 74LVC1G126 instead for 3.3 V operation.
Does the 74HCT1G126GW,125 have built-in power-on reset behavior for the output enable function?
No - OE is purely combinational. At power-up, OE state depends on external circuitry; if left floating, internal leakage may cause metastable output states. A 10 kΩ pull-down resistor on OE is recommended to guarantee Y = high-Z during startup until firmware asserts control.
How does the input clamp diode affect design when interfacing to a 12 V sensor signal?
The clamp diodes allow safe interface if a series current-limiting resistor restricts IIK to ≤±20 mA. For 12 V input, a 390 Ω resistor limits peak current to ~17.5 mA at VCC = 5 V, satisfying absolute maximum ratings while preserving signal integrity through the 3-state buffer path.
74HCT1G126GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HCT
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74HCT1G126GW,125 FAQ
1.How can I place an order for 74HCT1G126GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT1G126GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT1G126GW,125 reliable?
The price and inventory of 74HCT1G126GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT1G126GW,125 is usually 5 days.
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5.How can I obtain technical support or documentation for 74HCT1G126GW,125?
For technical support, including 74HCT1G126GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT1G126GW,125 requirements.
6.How does Aetrix verify that 74HCT1G126GW,125 is sourced from the original manufacturer or authorized distributors?
All 74HCT1G126GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT1G126GW,125 meets industry standards.
7.What is the process for return or replacement of 74HCT1G126GW,125?
All 74HCT1G126GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT1G126GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT1G126GW,125 part is unused and in its original packaging.
Return procedure for 74HCT1G126GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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