Nexperia USA Inc. 74HCT367D,652
- Part No.:
- 74HCT367D,652
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HCT367D,652.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:1,069
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Product details
Overview
74HCT367D,652 from Nexperia is a hex non-inverting 3-state buffer/line driver with TTL-compatible inputs and CMOS outputs, operating from 4.5 V to 5.5 V, delivering 6.0 mA output drive at VCC = 4.5 V, with propagation delay of 14 ns (typ) and enable/disable times under 35 ns - used in bus interface isolation and address/data line buffering in industrial microcontroller systems.
For engineers reviewing the 74HCT367D,652 datasheet, 74HCT367D,652 pinout, 74HCT367D,652 application, or 74HCT367D,652 equivalent, key selection criteria include TTL-level input compatibility, 3-state bus contention control, SO16 thermal derating above 110 °C, and guaranteed operation from –40 °C to +125 °C.
Technical Context
The 74HCT367D,652 implements six independent non-inverting buffers, each with active-low 3-state enable (1OE, 2OE), supporting bidirectional bus management via high-impedance OFF-state (Z) when enables are HIGH. Inputs accept standard TTL logic thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V at VCC = 4.5–5.5 V).
Its dynamic behavior is characterized by tpd = 14 ns (typ), ten = 16 ns (typ), and tdis = 21 ns (typ) at VCC = 4.5 V and CL = 50 pF, with input transition rate tolerance up to 139 ns/V at 4.5 V - enabling reliable timing in synchronous digital interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with 5 V TTL and mixed-voltage logic systems without level shifters. |
| Input Logic Type | TTL-level - accepts standard 0.8 V/2.0 V thresholds, eliminating need for external biasing on legacy 5 V controller buses. |
| Output Drive | ±6.0 mA at VCC = 4.5 V - sufficient to drive 10 LSTTL loads or 50 pF traces without signal degradation. |
| Propagation Delay | 14 ns (typ) at VCC = 4.5 V, CL = 50 pF - supports >30 MHz bus toggle rates in buffered address/data paths. |
| Operating Temp | –40 °C to +125 °C - qualified for extended-temperature industrial control, motor drives, and power supply monitoring. |
| Power Dissipation | 8.0 μA ICC (typ) per input at VCC = 5.5 V - enables low-quiescent-current standby states in battery-backed systems. |
| ESD Rating | HBM >2000 V, CDM >1000 V - provides robust handling during PCB assembly and field service without extra protection circuitry. |
Pinout & Package
74HCT367D,652 uses the SOT109-1 (SO16) plastic small outline package: 16-pin, 3.9 mm body width, 1.27 mm lead pitch, with gull-wing leads and pin 1 index marker. Thermal derating begins at 110 °C (12.4 mW/K).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - tie LOW to activate corresponding three buffers; tie HIGH to isolate bus segments. |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Data inputs - non-inverting logic inputs accepting TTL thresholds; clamp diodes allow safe overvoltage interface with current-limiting resistors. |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Buffered outputs - CMOS-compatible, 3-state capable; sink/source ±6 mA while maintaining VOL ≤ 0.26 V and VOH ≥ 3.98 V. |
| 8 | GND | Ground reference - must be connected to system 0 V plane; decoupling capacitor (100 nF) required within 5 mm of pin 8 and 16. |
| 16 | VCC | Supply voltage - connects to regulated 4.5–5.5 V rail; internal ESD protection and latch-up immunity (>100 mA) enhance system reliability. |
Key Features
| Feature | Design Value |
|---|---|
| 3-state bus control | Two independent enable inputs (1OE, 2OE) each controlling three buffers - enables flexible segmentation of 6-bit data/address buses without external logic. |
| TTL-compatible inputs | VIL ≤ 0.8 V, VIH ≥ 2.0 V at VCC = 4.5–5.5 V - eliminates need for level translators when interfacing with legacy 5 V microcontrollers or FPGAs. |
| High noise immunity | Typical noise margin >1.2 V at VCC = 4.5 V - suppresses false triggering from EMI in motor drive or switching power supply environments. |
| Clamp diode inputs | Integrated input clamping diodes - permit safe interface to signals exceeding VCC using series current-limiting resistors (e.g., 1 kΩ for 12 V inputs). |
| Extended temperature range | Specified from –40 °C to +125 °C - supports deployment in under-hood automotive ECUs, industrial PLCs, and outdoor telecom equipment. |
Applications
| Industrial Bus Isolation | Microcontroller Address Buffering |
|---|---|
|
Use Scenario: Isolating multiple peripheral modules (ADC, DAC, EEPROM) on a shared 8-bit data bus in an industrial PLC backplane. IC Role / Device Role / Timing Role: Hex buffer acts as direction-controlled bus gate; 1OE/2OE enable selective module access while preventing bus contention during read/write cycles. Use Value: Eliminates need for discrete MOSFET switches or complex CPLD logic; 14 ns propagation delay ensures timing compliance with 25 MHz bus clocks. |
Use Scenario: Driving 16-bit address lines from a Cortex-M4 MCU to external SRAM and flash memory in a medical imaging subsystem. IC Role / Device Role / Timing Role: Non-inverting buffer strengthens weak MCU address outputs; 3-state capability allows shared address bus with DMA controllers during burst transfers. Use Value: Maintains signal integrity across 10 cm PCB traces; ±6 mA drive sustains VIH > 2.0 V at all receivers even with 50 pF loading per line. |
| Legacy System Interface | Test Equipment Signal Conditioning |
|
Use Scenario: Interfacing modern ARM-based test controller with vintage 5 V TTL instrumentation (oscilloscopes, function generators) via GPIB or parallel port. IC Role / Device Role / Timing Role: Level-shifting buffer translates MCU GPIO logic to full TTL swing; clamp diodes protect against ±12 V instrument line transients. Use Value: Replaces discrete transistor arrays; TTL input compatibility avoids external pull-ups or Schmitt triggers on control lines. |
Use Scenario: Conditioning digital trigger and clock signals in automated test equipment (ATE) before routing to FPGA-based pattern generators. IC Role / Device Role / Timing Role: Low-skew buffer isolates sensitive FPGA inputs from noisy relay drivers and solenoid controls. Use Value: 5 ns transition time (tt) minimizes jitter accumulation; 125 °C rating permits placement near power supplies without thermal derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT367N | Dual-in-line (DIP-16) package; no thermal derating curve; max ambient 70 °C only. | Suitable for lab prototypes and breadboard evaluation, not for production in sealed enclosures or high-temp environments. | Select only for manual soldering or temporary validation; lacks SO16's reflow compatibility and extended temp support. |
| 74LVC367PW | 3.3 V only (1.65–3.6 V); LVCMOS inputs; lower drive (±24 mA), faster tpd = 4.2 ns. | Requires level translation when interfacing with 5 V systems; incompatible with direct TTL input sourcing. | Choose only for 3.3 V-only designs; unsuitable as drop-in replacement where 5 V tolerance or TTL input is required. |
Compared with SN74HCT367N and 74LVC367PW, the 74HCT367D,652 uniquely combines 5 V TTL compatibility, SO16 reflow readiness, and full –40 °C to +125 °C qualification - making it the sole option for volume-manufactured industrial controllers requiring long-term thermal stability and legacy interface support.
Availability
74HCT367D,652 is available at Aetrix Electronics and suitable for industrial bus isolation, microcontroller address buffering, legacy system interface, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HCT367D,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components with emphasis on reliability and energy efficiency.
The 74HCT367D,652 belongs to Nexperia's 74HCT logic family - engineered for seamless integration between TTL-based legacy systems and modern CMOS controllers, prioritizing noise immunity, wide voltage tolerance, and industrial-grade thermal performance.
FAQ
What is the maximum output current per pin for 74HCT367D,652?
The 74HCT367D,652 delivers ±6.0 mA DC output current per Y-output at VCC = 4.5 V, with VOL ≤ 0.26 V and VOH ≥ 3.98 V under those conditions. Absolute maximum output current is ±35 mA, but sustained operation above ±6 mA risks exceeding recommended operating limits and degrading timing or noise margins.
Can 74HCT367D,652 operate at 3.3 V supply?
No - the 74HCT367D,652 is specified only for 4.5 V to 5.5 V operation. At 3.3 V, input thresholds (VIH ≥ 2.0 V) remain valid, but VOH drops below 2.4 V and VOL rises above 0.4 V, violating TTL compatibility and risking downstream logic errors. Use 74LVC367 for 3.3 V systems.
How does the 3-state enable logic work on pins 1 and 15?
Pins 1 (1OE) and 15 (2OE) are active-low enables: a LOW signal activates the corresponding three buffers (1A→1Y, 2A→2Y, 3A→3Y for 1OE; 4A→4Y, 5A→5Y, 6A→6Y for 2OE), while a HIGH forces those outputs into high-impedance (Z) state. Both enables can be tied together or driven independently for granular bus control.
Is 74HCT367D,652 suitable for automotive applications?
No - the 74HCT367D,652 is not AEC-Q100 qualified and lacks automotive-specific testing (e.g., HTOL, EFT, ISO 11452). While its –40 °C to +125 °C rating covers under-hood temperatures, Nexperia explicitly states non-automotive qualification in its legal disclaimers; use 74HCT367-Q100 variants for automotive designs.
74HCT367D,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HCT
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
74HCT367D,652 FAQ
1.How can I place an order for 74HCT367D,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT367D,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT367D,652 reliable?
The price and inventory of 74HCT367D,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT367D,652 is usually 5 days.
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74HCT367D,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT367D,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT367D,652?
For technical support, including 74HCT367D,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT367D,652 requirements.
6.How does Aetrix verify that 74HCT367D,652 is sourced from the original manufacturer or authorized distributors?
All 74HCT367D,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT367D,652 meets industry standards.
7.What is the process for return or replacement of 74HCT367D,652?
All 74HCT367D,652 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT367D,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT367D,652 part is unused and in its original packaging.
Return procedure for 74HCT367D,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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