Nexperia USA Inc. 74HCT367DB,118
- Part No.:
- 74HCT367DB,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 16-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HCT367DB,118.pdf
- Description:
- IC BUF NON-INVERT 5.5V 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,166
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HCT367DB,118 from Nexperia is a hex non-inverting 3-state buffer/line driver with TTL-compatible inputs and CMOS outputs, operating from 4.5 V to 5.5 V supply, delivering 6.0 mA output drive at VCC = 4.5 V, and supporting industrial temperature range (−40 °C to +125 °C) in SO16 package - used for bus interface isolation and address/data line driving in microcontroller peripheral expansion systems.
For engineers reviewing the 74HCT367DB,118 datasheet, 74HCT367DB,118 pinout, 74HCT367DB,118 application, or 74HCT367DB,118 equivalent, key selection criteria include TTL-level input compatibility, 3-state enable timing (ten = 16–53 ns), output drive capability (±6 mA), thermal derating behavior (12.4 mW/K above 110 °C), and SO16 mechanical footprint compliance with JEDEC MS-012.
Technical Context
The 74HCT367DB,118 implements six independent non-inverting buffers, each with active-low 3-state control via dedicated OE pins (1OE on pin 1, 2OE on pin 15). Its TTL-compatible input thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V at VCC = 4.5–5.5 V) ensure direct interfacing with legacy 5 V logic families without level shifting.
Output switching is characterized by propagation delay tpd = 14–38 ns (VCC = 4.5 V, CL = 50 pF), enable/disable times of 16–53 ns, and transition time tt = 5–18 ns. Input clamping diodes allow safe overvoltage tolerance up to VCC + 0.5 V when used with current-limiting resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5 V TTL and mixed-voltage systems without regulator overhead. |
| Input Logic Type | TTL-level - accepts 0.8 V max low and 2.0 V min high, enabling direct connection to 74LS, 74F, and microcontroller GPIOs without translation. |
| Output Drive | ±6.0 mA at VCC = 4.5 V - sufficient to drive 10 LS-TTL loads or terminate short PCB traces without external buffers. |
| Propagation Delay | 14 ns (typ), 38 ns (max) at VCC = 4.5 V, CL = 50 pF - supports reliable operation in 25 MHz bus environments with margin. |
| 3-State Enable Time | 16 ns (typ), 53 ns (max) - defines minimum dead-time required between bus ownership handoffs in shared-data applications. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive modules, industrial PLC I/O cards, and high-reliability embedded controllers. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - meets IEC 61000-4-2 Level 2 requirements for handling robustness in assembly and field service. |
Pinout & Package
74HCT367DB,118 is housed in SOT109-1 (SO16), a plastic small outline package with 16 leads, 3.9 mm body width, and JEDEC MS-012 compliant footprint - suitable for automated SMT placement and reflow soldering per IPC-J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - each controls three outputs; pulling either LOW enables its associated buffer group, HIGH places outputs in high-Z. |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Buffer data inputs - non-inverting; accept TTL-level signals and drive corresponding Y outputs with CMOS swing. |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Buffer outputs - CMOS-compatible, rail-to-rail swing, capable of sourcing/sinking ±6 mA into capacitive or resistive loads. |
| 8 | GND | Ground reference - must be low-inductance connection to system ground plane to minimize noise coupling during switching. |
| 16 | VCC | Positive supply - requires local 100 nF ceramic decoupling capacitor placed within 5 mm of pin to suppress supply transients. |
Key Features
| Feature | Design Value |
|---|---|
| Wide supply range | 4.5 V to 5.5 V - eliminates need for precision 5.0 V regulation; tolerates ±5 % rail variation in noisy industrial power domains. |
| Input clamp diodes | Integrated bidirectional ESD protection - allows use of series current-limiting resistors to safely interface inputs to voltages up to VCC + 0.5 V. |
| High noise immunity | Typical 40 % VCC noise margin - ensures stable operation in electrically noisy environments such as motor drives and relay panels. |
| Latch-up immunity | > 100 mA per JESD78 Class II Level B - prevents destructive latch-up during transient overvoltage or hot-swap events. |
| Low static current | ≤ 160 μA at +125 °C - minimizes quiescent power in always-on monitoring circuits and battery-backed subsystems. |
Applications
| Microcontroller Bus Expansion | Industrial I/O Module |
|---|---|
|
Use Scenario: Expanding GPIO count of an ARM Cortex-M4 MCU to drive 16-bit parallel LCD interface and keypad scan matrix. IC Role / Device Role / Timing Role: Hex buffer isolates MCU pins from bus capacitance and provides level-consistent drive; dual OE pins enable interleaved access to display and keypad sections. Use Value: Enables deterministic timing control (ten/tdis ≤ 53 ns) and eliminates signal integrity degradation across 10 cm PCB traces loaded with 30 pF per segment. |
Use Scenario: Isolating digital output channels in a programmable logic controller (PLC) rack module with hot-swap capability. IC Role / Device Role / Timing Role: 3-state outputs prevent back-driving during module insertion/removal; OE pins synchronized to backplane reset sequence. Use Value: Prevents bus contention during live insertion; ±6 mA drive sustains 24 V optocoupler LED bias through 1 kΩ current-limiting resistors. |
| Legacy System Interface Adapter | Test Equipment Signal Conditioning |
|
Use Scenario: Bridging 5 V TTL address/data bus of vintage test equipment to modern FPGA-based controller board. IC Role / Device Role / Timing Role: Acts as bidirectional level-tolerant buffer; TTL inputs accept original equipment's 0.8 V/2.0 V thresholds while driving FPGA I/O banks at full CMOS swing. Use Value: Eliminates need for discrete level shifters; 14 ns typical tpd preserves setup/hold margins for 20 MHz synchronous transfers. |
Use Scenario: Driving multiple DUT (device-under-test) inputs simultaneously from a single pattern generator channel in ATE systems. IC Role / Device Role / Timing Role: Fan-out buffer with controlled edge rates (tt = 5–18 ns); 3-state capability allows dynamic reconfiguration of stimulus paths. Use Value: Reduces pattern generator channel count by 6×; low output skew (<1 ns) ensures simultaneous assertion across all DUT inputs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT367N | Dual in-line package (PDIP-16); no thermal derating curve specified; identical electrical specs. | Suitable only for prototyping or through-hole production; lacks SO16's reflow compatibility and board space efficiency. | Select when manual assembly or breadboard validation is required; avoid for volume SMT manufacturing. |
| 74LVC367APW | 3.3 V only (1.65–3.6 V); lower drive (±24 mA); faster tpd (3.4 ns typ); TSSOP16 package. | Requires level translation for 5 V systems; unsuitable for direct replacement without redesign. | Choose only for new 3.3 V designs prioritizing speed and density; not a drop-in substitute for 74HCT367DB,118. |
Compared with SN74HCT367N and 74LVC367APW, the 74HCT367DB,118 uniquely balances 5 V TTL interoperability, SO16 manufacturability, and −40 °C to +125 °C qualification - making it the sole option for high-volume, thermally demanding, surface-mount 5 V bus interface applications.
Availability
74HCT367DB,118 is available at Aetrix Electronics and suitable for industrial PLC I/O modules, microcontroller peripheral expansion boards, legacy system interface adapters, and automated test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HCT367DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable components for automotive, industrial, and consumer applications - with leadership in logic, MOSFETs, diodes, and ESD protection.
The 74HCT367DB,118 belongs to Nexperia's 74HCT logic family, engineered specifically for robust 5 V TTL-to-CMOS interfacing in harsh environments where reliability, wide temperature operation, and noise immunity are critical design requirements.
FAQ
What is the maximum clock frequency supported by the 74HCT367DB,118?
The 74HCT367DB,118 is not a clocked device but a combinational buffer; its usable frequency depends on propagation delay and load. With tpd ≤ 38 ns and proper termination, it reliably supports data rates up to 25 MHz on 50 pF buses. For higher speeds, verify signal integrity using measured tt (5–18 ns) and board-level eye diagrams.
Can 74HCT367DB,118 drive LEDs directly?
Yes - each output can sink or source up to ±6.0 mA at VCC = 4.5 V, sufficient to drive low-current indicator LEDs (e.g., 2 mA @ 1.8 V forward voltage) with a series resistor. Do not exceed IO = ±35 mA total per package (summed across all active outputs) to stay within absolute maximum ratings.
Is the 74HCT367DB,118 pin-compatible with the 74HC367DB?
Yes - both share identical pinout (SOT109-1), function table, and package dimensions. However, the 74HC367DB uses CMOS-level inputs (VIH ≥ 3.15 V at VCC = 4.5 V), making it incompatible with TTL sources unless pulled up. The 74HCT367DB,118 is the correct choice for true TTL input compatibility.
Does 74HCT367DB,118 require external pull-up resistors on OE pins?
No - OE pins are active-low and internally referenced; they operate correctly with direct connection to GND (enable) or VCC (disable). Pull-up resistors are unnecessary and may slow disable timing. If OE must be controlled by open-drain logic, a 10 kΩ pull-up to VCC is acceptable but not required.
74HCT367DB,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HCT
- Package/Case:
- 16-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
74HCT367DB,118 FAQ
1.How can I place an order for 74HCT367DB,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT367DB,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT367DB,118 reliable?
The price and inventory of 74HCT367DB,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT367DB,118 is usually 5 days.
3.What payment methods are accepted for 74HCT367DB,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT367DB,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HCT367DB,118?
74HCT367DB,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT367DB,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT367DB,118?
For technical support, including 74HCT367DB,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT367DB,118 requirements.
6.How does Aetrix verify that 74HCT367DB,118 is sourced from the original manufacturer or authorized distributors?
All 74HCT367DB,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT367DB,118 meets industry standards.
7.What is the process for return or replacement of 74HCT367DB,118?
All 74HCT367DB,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT367DB,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT367DB,118 part is unused and in its original packaging.
Return procedure for 74HCT367DB,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HCT367DB,118 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

