Nexperia USA Inc. 74HCT367PW,112
- Part No.:
- 74HCT367PW,112
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74HCT367PW,112.pdf
- Description:
- IC BUF NON-INVERT 5.5V 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74HCT367PW,112 from Nexperia is a hex non-inverting 3-state buffer/line driver with TTL-compatible inputs and CMOS outputs, operating from 4.5 V to 5.5 V supply, delivering 6.0 mA output drive at VCC = 4.5 V, and supporting industrial temperature range (−40 °C to +125 °C) in TSSOP16 package for bus interface isolation in microcontroller peripheral expansion.
For engineers reviewing the 74HCT367PW,112 datasheet, 74HCT367PW,112 pinout, 74HCT367PW,112 application, or 74HCT367PW,112 equivalent, key selection criteria include TTL-level input compatibility, 3-state enable timing (ten ≤ 38 ns max), propagation delay (tpd ≤ 38 ns max), low static current (ICC ≤ 160 μA), and thermal derating behavior above +91 °C.
Technical Context
This device implements six independent non-inverting buffers, each with active-low 3-state output control via dedicated OE pins (1OE on pin 1, 2OE on pin 15). The logic function follows standard truth table: when OE is LOW, Y = A; when OE is HIGH, Y = high-impedance Z.
Input clamping diodes allow safe interfacing to voltages exceeding VCC using external current-limiting resistors. Static characteristics are specified across −40 °C to +125 °C, with VIH = 2.0 V min and VIL = 0.8 V max at VCC = 4.5–5.5 V, ensuring robust TTL-level recognition.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with 5 V TTL and mixed-voltage systems without level shifters |
| Input Logic Type | TTL-level - accepts standard 5 V logic thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) |
| Output Drive | ±6.0 mA at VCC = 4.5 V - sufficient to drive 50 pF loads with <38 ns propagation delay |
| 3-State Enable Time | ten ≤ 38 ns max - enables fast bus arbitration in multiplexed data paths |
| Operating Temperature | −40 °C to +125 °C - supports under-hood and industrial control environments |
| Power Dissipation | Ptot = 500 mW (derates 8.5 mW/K above +91 °C) - defines thermal design margin in TSSOP16 |
| Input Capacitance | CI = 3.5 pF - minimizes capacitive loading on driving sources |
Pinout & Package
TSSOP16 plastic thin shrink small outline package (SOT403-1), 16-pin, body width 4.4 mm, lead pitch 0.65 mm, exposed pad not present, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - simultaneous assertion disables all six outputs to high-Z |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Buffer data inputs - six independent logic inputs accepting TTL-level signals |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Non-inverting buffered outputs - each mirrors its A input when respective OE is LOW |
| 8 | GND | Ground reference - must be connected to system 0 V plane for noise immunity and correct logic levels |
| 16 | VCC | Positive supply - powers internal CMOS circuitry; decoupling capacitor required near pin |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible inputs | VIH = 2.0 V min, VIL = 0.8 V max at VCC = 4.5–5.5 V - eliminates need for external level translation in legacy 5 V systems |
| Clamp diode protection | Enables safe overvoltage input handling up to ±20 mA - permits direct connection to higher-voltage buses with series resistors |
| Low quiescent current | ICC ≤ 160 μA at +125 °C - reduces standby power in always-on industrial controllers |
| Fast 3-state switching | ten/tdis ≤ 38 ns max - supports >10 MHz bus toggle rates in shared-data applications |
| ESD robustness | HBM > 2000 V, CDM > 1000 V - improves manufacturing yield and field reliability in uncontrolled ESD environments |
Applications
| Microcontroller I/O Expansion | Industrial Bus Isolation |
|---|---|
Use Scenario: Expanding GPIO count of an ARM Cortex-M4 MCU to drive 16-bit parallel LCD interface while sharing address/data bus with SPI peripherals. IC Role / Device Role / Timing Role: Acts as bidirectional bus buffer with independent OE control, isolating LCD data lines during SPI transfers to prevent contention. Use Value: Enables deterministic timing with tpd ≤ 38 ns and tdis ≤ 38 ns, eliminating bus glitches during mode switching. | Use Scenario: Isolating Modbus RTU RS-485 transceiver data lines from PLC main CPU to suppress ground loop noise and transient coupling. IC Role / Device Role / Timing Role: Provides unidirectional signal buffering with 3-state capability, allowing clean enable/disable of transceiver control path during fault recovery. Use Value: Input clamp diodes tolerate ±15 V transients; 6 mA drive sustains 1200 m cable runs at 115.2 kbps. |
| Legacy System Interfacing | Test Equipment Signal Conditioning |
Use Scenario: Interfacing modern FPGA-based test controller to vintage 1980s TTL instrumentation with 5 V logic and 10 mA fan-out requirements. IC Role / Device Role / Timing Role: Bridges voltage and current domain mismatch - accepts TTL inputs and drives legacy TTL loads without pull-up resistors. Use Value: Guaranteed VIH/VIL margins ensure reliable recognition of marginal TTL waveforms; 6 mA sink/source meets SN74LSxx fan-out specs. | Use Scenario: Routing calibrated analog-to-digital conversion trigger signals through a multi-channel automated test system with variable channel enable sequencing. IC Role / Device Role / Timing Role: Serves as digitally controlled gate for synchronous trigger distribution, where 3-state outputs prevent signal contention across parallel channels. Use Value: Low 3.5 pF input capacitance preserves edge integrity; sub-40 ns enable timing aligns triggers within 1 LSB of 25 MHz sampling clock. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT367N | Dual in-line package (PDIP-16); no thermal derating curve published; wider body (6.35 mm) | Better suited for prototyping and through-hole PCBs; lower thermal performance in high-density layouts | Select for hand-soldered evaluation or legacy board rework where TSSOP reflow is unavailable |
| 74LVC367PW | Lower VCC range (1.65–3.6 V); LVTTL-compatible inputs; 24 mA drive; smaller 3.5 pF CI | Designed for 3.3 V systems only; incompatible with 5 V TTL input sources without level shifting | Choose only for new 3.3 V designs requiring higher drive strength and lower capacitance |
Compared with SN74HCT367N and 74LVC367PW, the 74HCT367PW,112 uniquely balances 5 V TTL interoperability, TSSOP thermal efficiency, and industrial temperature support - making it optimal for space-constrained, high-reliability 5 V embedded interfaces.
Availability
74HCT367PW,112 is available at Aetrix Electronics and suitable for microcontroller I/O expansion, industrial bus isolation, legacy system interfacing, and test equipment signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74HCT367PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components, headquartered in Nijmegen, Netherlands.
The 74HCT series belongs to Nexperia's industry-standard logic portfolio, engineered for interoperability between TTL and CMOS systems in industrial, computing, and communications infrastructure.
FAQ
What is the maximum recommended operating frequency for 74HCT367PW,112 in a 50 pF load configuration?
The device does not specify a maximum clock frequency, but dynamic characteristics show tpd ≤ 38 ns and tdis/ten ≤ 38 ns at VCC = 4.5 V and CL = 50 pF. This supports reliable operation up to approximately 10 MHz for bus toggling, assuming setup/hold margins and PCB trace delays are accounted for in layout.
Can 74HCT367PW,112 safely interface with 3.3 V logic inputs?
No - its TTL-compatible inputs require VIH ≥ 2.0 V minimum, but are only guaranteed functional at VCC = 4.5–5.5 V. Driving it from a 3.3 V source risks marginal VIH recognition; use 74LVC367PW or level translators instead for 3.3 V–5 V bridging.
Does 74HCT367PW,112 support hot insertion or live bus swapping?
It features input clamp diodes rated for ±20 mA, enabling limited hot-swap tolerance when used with appropriate series current-limiting resistors (e.g., 1 kΩ). However, full hot-swap compliance requires additional protection circuitry per IEC 61000-4-2, as the device lacks dedicated hot-swap control logic.
How does the thermal derating of 74HCT367PW,112 affect its maximum continuous power dissipation?
In its TSSOP16 (SOT403-1) package, Ptot = 500 mW up to +91 °C, then derates linearly by 8.5 mW/K. At +125 °C ambient, maximum allowable dissipation drops to 500 − (125 − 91) × 8.5 ≈ 211 mW - requiring careful thermal design in sealed enclosures or high-power-density layouts.
74HCT367PW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HCT
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
74HCT367PW,112 FAQ
1.How can I place an order for 74HCT367PW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT367PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of 74HCT367PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT367PW,112 is usually 5 days.
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5.How can I obtain technical support or documentation for 74HCT367PW,112?
For technical support, including 74HCT367PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT367PW,112 requirements.
6.How does Aetrix verify that 74HCT367PW,112 is sourced from the original manufacturer or authorized distributors?
All 74HCT367PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT367PW,112 meets industry standards.
7.What is the process for return or replacement of 74HCT367PW,112?
All 74HCT367PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT367PW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT367PW,112 part is unused and in its original packaging.
Return procedure for 74HCT367PW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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