NXP Semiconductors 74HCT4053D,112
- Part No.:
- 74HCT4053D,112
- Manufacturer:
- NXP Semiconductors
- Package:
- -
- Datasheet:
-
74HCT4053D,112.pdf
- Description:
- NEXPERIA 74HCT4053D - SINGLE-END
- Quantity:
- Payment:

- Shipping:

Inventory:12,841
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HCT4053D,112 from Nexperia is a triple 2-channel analog multiplexer/demultiplexer (3×SPDT) designed for bidirectional signal routing in mixed-signal systems. It features independent 1Y0/1Y1, 2Y0/2Y1, and 3Y0/3Y1 inputs/outputs with common terminals 1Z/2Z/3Z, digital select inputs S1–S3, and a shared active-low enable input E. With ±5 V analog voltage range, 70 Ω typical ON resistance at 4.5 V supply, and operation from –40 °C to +125 °C, it supports precision analog switching in industrial sensor interfaces and test equipment.
For engineers reviewing the 74HCT4053D,112 datasheet, 74HCT4053D,112 pinout, 74HCT4053D,112 application, or 74HCT4053D,112 equivalent, key selection criteria include its TTL-compatible logic inputs (VIH = 2.0 V min), rail-to-rail analog switching capability across VEE = –5 V to VCC = +5.5 V, break-before-make timing, and SO16 package compatibility with legacy PCB layouts.
Technical Context
The 74HCT4053D,112 implements three independent single-pole double-throw (SPDT) analog switches controlled by CMOS logic-level inputs. Each switch operates bidirectionally between its two independent terminals (nY0/nY1) and a common terminal (nZ), with channel selection determined by Sn and global state controlled by active-low E.
It uses standard silicon CMOS process technology with integrated clamp diodes on all digital inputs, enabling safe interfacing to voltages exceeding VCC when used with current-limiting resistors. The device supports dual-supply operation (VCC and VEE), allowing true bipolar analog signal handling from –5 V to +5 V while maintaining TTL-compatible digital control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Triple SPDT analog switch - enables three independent 2:1 analog MUX/DEMUX paths in one IC |
| Analog Voltage Range | –5 V to +5 V - supports full bipolar signal routing without level-shifting circuitry |
| ON Resistance (typ) | 70 Ω at VCC = 4.5 V, VEE = –4.5 V - ensures low insertion loss for audio and sensor signals |
| Logic Compatibility | TTL-input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V @ VCC = 4.5–5.5 V) - directly drives from 5 V microcontrollers |
| Propagation Delay | 4 ns typ (Vis→Vos, VCC = 4.5 V, VEE = –4.5 V) - suitable for <100 MHz analog sampling control |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive and industrial control environments |
| Isolation (OFF-state) | –50 dB @ 1 MHz - minimizes crosstalk between inactive channels in multi-sensor systems |
Pinout & Package
74HCT4053D,112 is supplied in SO16 (SOT109-1) package: plastic small outline, 16-pin, 3.9 mm body width, surface-mount.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 2Y1 | Independent terminal of second switch - connects to selected signal source/sink when S2 = HIGH |
| 2 | 2Y0 | Independent terminal of second switch - connects to selected signal source/sink when S2 = LOW |
| 3 | 3Y1 | Independent terminal of third switch - connects to selected signal source/sink when S3 = HIGH |
| 4 | 3Z | Common terminal of third switch - bidirectional path shared between 3Y0 and 3Y1 |
| 5 | 3Y0 | Independent terminal of third switch - connects to selected signal source/sink when S3 = LOW |
| 6 | E | Active-low enable - all switches OFF when HIGH; required for power-gating and system-level sleep control |
| 7 | VEE | Negative supply rail - sets lower bound of analog voltage range; must be connected for bipolar operation |
| 8 | GND | Digital ground reference - separate from VEE in dual-supply configurations; return path for logic inputs |
| 9 | S3 | Select input for third switch - controls connection between 3Y0/3Y1 and 3Z; TTL-compatible |
| 10 | S2 | Select input for second switch - controls connection between 2Y0/2Y1 and 2Z; TTL-compatible |
| 11 | S1 | Select input for first switch - controls connection between 1Y0/1Y1 and 1Z; TTL-compatible |
| 12 | 1Y0 | Independent terminal of first switch - connects to selected signal source/sink when S1 = LOW |
| 13 | 1Y1 | Independent terminal of first switch - connects to selected signal source/sink when S1 = HIGH |
| 14 | 1Z | Common terminal of first switch - bidirectional path shared between 1Y0 and 1Y1 |
| 15 | 2Z | Common terminal of second switch - bidirectional path shared between 2Y0 and 2Y1 |
| 16 | VCC | Positive supply rail - powers internal logic and defines upper analog voltage limit (max +5.5 V) |
Key Features
| Feature | Design Value |
|---|---|
| Break-before-make switching | Prevents momentary shorting between Y0 and Y1 during channel transitions - critical for avoiding signal glitches in data acquisition |
| Logic-level translation | Accepts 5 V TTL logic inputs while switching ±5 V analog signals - eliminates external level shifters in mixed-voltage systems |
| Low ON-resistance mismatch | ΔRON ≤ 6 Ω (typ) - ensures matched gain/attenuation across channels in multi-path instrumentation |
| Bipolar analog support | VEE pin enables true dual-supply operation down to –5 V - required for AC-coupled audio, op-amp feedback, and sensor biasing |
| ESD robustness | HBM > 2000 V, CDM > 1000 V - withstands handling and board-level ESD events without latch-up or parameter shift |
Applications
| Industrial Sensor Multiplexing | Automotive Diagnostic Interface |
|---|---|
Use Scenario: Routing outputs from 6 RTD or thermocouple sensors to a single ADC in programmable logic controller (PLC) backplane. IC Role / Device Role / Timing Role: Analog MUX front-end - sequentially connects each sensor's differential output to ADC inputs under microcontroller GPIO control. Use Value: Reduces BOM cost and PCB area vs. discrete analog switches; ±5 V range accommodates sensor offset voltages without clamping. |
Use Scenario: Selecting between multiple CAN transceiver diagnostic lines (K-line, L-line, ISO 9141) in vehicle OBD-II gateway module. IC Role / Device Role / Timing Role: Signal gating element - isolates unused diagnostic bus lines to prevent noise coupling and meet ISO 11898-2 stub length requirements. Use Value: Enables single microcontroller UART to service multiple legacy protocols; TTL-compatible inputs simplify interface to 5 V automotive MCUs. |
| Audio Signal Routing | Programmable Instrumentation Front-End |
Use Scenario: Switching between line-in, mic-in, and headphone-out paths in portable audio analyzer with dual-channel codec. IC Role / Device Role / Timing Role: Bidirectional analog switch matrix - routes audio signals in both directions (input and output) using same 74HCT4053D,112 channels. Use Value: 70 Ω ON resistance and <0.02% sine-wave distortion preserve THD+N performance; SO16 footprint allows compact layout near codec IC. |
Use Scenario: Configuring gain, filter cutoff, and signal path in modular benchtop multimeter with user-selectable measurement ranges. IC Role / Device Role / Timing Role: Precision analog path selector - connects calibration references, attenuators, and amplifier stages under firmware control. Use Value: –40 °C to +125 °C rating ensures stability across environmental test chambers; low leakage (<0.1 μA OFF-state) prevents DC error accumulation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HC4053D,112 | CMOS logic inputs (VIH = 3.15 V min @ VCC = 4.5 V); wider VCC range (2–10 V) | Better suited for mixed 3.3 V/5 V systems where logic supply varies | Choose when interfacing to 3.3 V controllers or requiring extended supply flexibility |
| ADG1433BRUZ | Single-supply only (±15 V max); higher ON resistance (1.3 Ω typ); SPI-controlled | Requires external level-shifting for 5 V logic; adds firmware overhead but enables daisy-chained configuration | Choose when ultra-low RON or SPI configurability outweighs added complexity and cost |
Compared with 74HC4053D,112 and ADG1433BRUZ, the 74HCT4053D,112 provides optimal balance of TTL compatibility, bipolar analog range, and SO16 footprint - making it ideal for cost-sensitive industrial designs where 5 V microcontrollers control analog signal paths without SPI infrastructure.
Availability
74HCT4053D,112 is available at Aetrix Electronics and suitable for industrial automation, automotive diagnostics, and portable instrumentation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HCT4053D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance logic, analog, and discrete components, with global manufacturing and quality certification to IATF 16949 and ISO 9001 standards.
The 74HCT4053D,112 belongs to Nexperia's 74HCT logic family - engineered for TTL-compatible operation in industrial and automotive systems where robustness, wide temperature range, and analog signal integrity are critical.
FAQ
What is the maximum analog signal voltage range supported by the 74HCT4053D,112?
The 74HCT4053D,112 supports analog signals from VEE to VCC. With VCC = +5.5 V and VEE = –5 V, it handles true bipolar signals from –5 V to +5.5 V. This range is guaranteed per datasheet Table 5 and enables direct connection to op-amp outputs, sensor bridges, and audio codecs without external level shifting. Operation outside this range risks damage or undefined behavior.
Does the 74HCT4053D,112 require pull-up or pull-down resistors on its S1–S3 and E pins?
No, the 74HCT4053D,112 does not require external pull-up or pull-down resistors on S1–S3 or E. Its TTL-compatible inputs have defined VIH (≥2.0 V) and VIL (≤0.8 V) thresholds at VCC = 4.5–5.5 V, and internal input structures ensure stable logic states when driven directly from microcontroller GPIOs. External resistors are only needed if driving from open-drain sources or high-impedance nodes.
Can the 74HCT4053D,112 be used with a single 5 V supply (VEE = GND)?
Yes, the 74HCT4053D,112 functions with VEE = GND and VCC = 4.5–5.5 V. In this configuration, it switches analog signals from 0 V to VCC, supporting unipolar applications like digital I/O expansion or 0–5 V sensor multiplexing. However, the full ±5 V range requires separate VEE = –5 V connection - confirmed in datasheet Figures 5 and 6 operating area plots.
What is the typical ON-resistance mismatch between channels in the 74HCT4053D,112?
The 74HCT4053D,112 exhibits ΔRON ≤ 6 Ω (typical) between any two channels at VCC = 4.5 V and VEE = –4.5 V, as specified in Table 6. This tight matching ensures consistent gain, attenuation, and time-domain response across all three SPDT switches - essential for precision applications such as multi-channel data acquisition and calibrated test equipment where channel-to-channel uniformity is critical.
How does the break-before-make timing affect signal integrity in the 74HCT4053D,112?
The 74HCT4053D,112 incorporates built-in break-before-make timing, ensuring that one channel disconnects fully before the other connects. This prevents momentary shorting between Y0 and Y1 terminals during switching - eliminating signal glitches, cross-talk spikes, and potential damage in circuits with conflicting voltage sources. Measured turn-off time (toff) is ≤31 ns (typ) at VCC = 4.5 V/VEE = –4.5 V, guaranteeing clean transitions even at 10 MHz control rates.
74HCT4053D,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Switch Circuit:
- -
- Multiplexer/Demultiplexer Circuit:
- -
- Number of Circuits:
- -
- On-State Resistance (Max):
- -
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- -
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- -
- Current - Leakage (IS(off)) (Max):
- -
- Crosstalk:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
74HCT4053D,112 FAQ
1.How can I place an order for 74HCT4053D,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT4053D,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT4053D,112 reliable?
The price and inventory of 74HCT4053D,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT4053D,112 is usually 5 days.
3.What payment methods are accepted for 74HCT4053D,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT4053D,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HCT4053D,112?
74HCT4053D,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT4053D,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT4053D,112?
For technical support, including 74HCT4053D,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT4053D,112 requirements.
6.How does Aetrix verify that 74HCT4053D,112 is sourced from the original manufacturer or authorized distributors?
All 74HCT4053D,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT4053D,112 meets industry standards.
7.What is the process for return or replacement of 74HCT4053D,112?
All 74HCT4053D,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT4053D,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT4053D,112 part is unused and in its original packaging.
Return procedure for 74HCT4053D,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HCT4053D,112 Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

