NXP Semiconductors 74HCT4067N,112
- Part No.:
- 74HCT4067N,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 24-DIP (0.600", 15.24mm)
- Datasheet:
-
74HCT4067N,112.pdf
- Description:
- IC MUX 16:1 120OHM 24DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,503
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HCT4067N,112 from NXP Semiconductors is a 16-channel analog multiplexer/demultiplexer with TTL-compatible inputs, 4-bit address decoding (S0–S3), active-low enable (E), 16 bidirectional Yn terminals, and one common Z terminal. It operates at 4.5 V to 5.5 V, delivers ≤70 Ω typical ON resistance at 5 V, supports ±25 mA switch current, and functions across −40 °C to +125 °C for industrial sensor signal routing.
For engineers reviewing the 74HCT4067N,112 datasheet, 74HCT4067N,112 pinout, 74HCT4067N,112 application, or 74HCT4067N,112 equivalent, key selection criteria include its 5 V logic compatibility, low ON-resistance matching across channels, break-before-make switching behavior, and DIP24 package suitability for prototyping and legacy PCB layouts.
Technical Context
The 74HCT4067N,112 implements sixteen independent CMOS transmission gates controlled by a 4-to-16 binary decoder. Its enable input (E) overrides address lines: when E = HIGH, all switches are OFF regardless of S0–S3; when E = LOW, exactly one Yn–Z path is closed per address code.
Each switch exhibits symmetrical analog conduction (bidirectional), supports rail-to-rail voltage swing (GND to VCC), and maintains <±1.0 µA OFF-state leakage at 5.5 V. The device complies with JEDEC standard no. 7A and features built-in break-before-make timing to prevent channel shorting during address transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5 V TTL logic systems and stable operation under industrial supply variation. |
| ON Resistance (typ) | 70 Ω at VCC = 5 V - enables low insertion loss for analog signals up to ~10 kHz without significant attenuation or distortion. |
| Switch Current | ±25 mA - supports direct interfacing with op-amp outputs, ADC inputs, and low-power sensors without external buffering. |
| Propagation Delay | 6 ns (Z→Yn, typ at 5 V) - suitable for multiplexing digital control signals and medium-speed serial data paths. |
| OFF-State Leakage | ±0.1 µA per channel at 5.5 V - preserves signal integrity in high-impedance sensor networks and precision measurement front-ends. |
| Operating Temp | −40 °C to +125 °C - validated for use in automotive engine control modules, industrial PLC I/O cards, and outdoor instrumentation. |
| Input Compatibility | TTL-level - accepts standard 5 V logic thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V), eliminating level-shifting requirements in mixed-logic systems. |
Pinout & Package
DIP24 plastic dual in-line package (SOT101-1), 24-pin through-hole, 600 mil width, reverse bending lead form, suitable for breadboarding and wave-soldered industrial assemblies.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Z) | Common I/O | Shared analog path for all 16 channels; must be routed with controlled impedance if handling >1 MHz signals due to 45 pF capacitance. |
| 2–9, 16–23 (Y0–Y15) | Independent I/O | 16 bidirectional analog/digital terminals; each connects to Z only when selected, otherwise presents >10⁹ Ω isolation. |
| 10, 11, 13, 14 (S0–S3) | Address Inputs | Binary-select lines determining which Yn connects to Z; TTL-compatible, require pull-up/down only if floating in system. |
| 12 (GND) | Ground Reference | Primary return path for logic and analog currents; must be low-inductance connection to minimize crosstalk between channels. |
| 15 (E) | Enable Input | Active-low global control: drives all switches OFF when HIGH, enabling synchronized channel disabling in multi-device systems. |
| 24 (VCC) | Supply Voltage | 5 V power rail; requires local 100 nF ceramic decoupling adjacent to pin to suppress switching noise coupling into analog paths. |
Key Features
| Feature | Design Value |
|---|---|
| Low ON Resistance | 70 Ω typical at 5 V - reduces voltage drop and thermal drift in precision analog multiplexing (e.g., thermocouple scanning). |
| Break-Before-Make Switching | Guaranteed non-overlapping conduction - prevents momentary short-circuits between Yn channels during address changes, critical for fault-tolerant sensor arrays. |
| Rail-to-Rail Analog Range | GND to VCC - allows full utilization of ADC input range without clamping diodes or external biasing networks. |
| TTL-Compatible Inputs | VIH ≥ 2.0 V, VIL ≤ 0.8 V - interfaces directly with microcontroller GPIOs, FPGA I/O banks, and legacy 5 V logic without level translators. |
| High OFF-State Isolation | −50 dB at 1 MHz - suppresses crosstalk between unselected channels, enabling reliable simultaneous sampling of multiple low-level sensor outputs. |
Applications
| Industrial Sensor Multiplexing | Automotive Diagnostic Interface |
|---|---|
Use Scenario: Scanning 12 temperature sensors on an HVAC controller PCB using a single 12-bit ADC input. IC Role / Device Role / Timing Role: Analog multiplexer routing thermistor voltages sequentially to ADC, with E pin synchronized to ADC conversion start pulse. Use Value: Reduces BOM count by eliminating 11 extra ADC channels while maintaining <0.1% gain error due to matched 70 Ω RON. | Use Scenario: Sharing a CAN transceiver's diagnostic test point among 8 ECU submodules during factory calibration. IC Role / Device Role / Timing Role: Digital demultiplexer isolating test signals to individual ECUs; S0–S3 driven by microcontroller GPIOs, E tied to test-mode enable. Use Value: Enables shared physical test port without signal contention, leveraging <±0.1 µA leakage to prevent backfeeding between modules. |
| Programmable Logic I/O Expansion | Audio Signal Routing |
Use Scenario: Expanding GPIO count on a PIC16F microcontroller to drive 16 relays via ULN2003 drivers. IC Role / Device Role / Timing Role: Digital multiplexer selecting one of 16 relay control lines; Z connected to microcontroller output, Yn to relay driver inputs. Use Value: Achieves 16-output expansion with only 5 control pins (S0–S3 + E), avoiding I²C port-expander latency and firmware overhead. | Use Scenario: Routing line-level audio from 16 studio inputs to a single analog compressor circuit. IC Role / Device Role / Timing Role: Analog multiplexer switching stereo signals; Z connected to compressor input, Yn to balanced XLR receivers with DC-blocking caps. Use Value: Maintains <0.04% THD at 1 kHz due to low RON and symmetric switch structure, preserving audio fidelity across all channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD74HC4067M96 | Same 16-channel architecture but HC logic family (2–6 V supply); 80 Ω RON at 4.5 V vs. 70 Ω for HCT. | Requires 4.5–6 V supply; less tolerant of 5 V TTL input noise margins than HCT variant. | Select when operating from 3.3 V or mixed-voltage systems where HC logic thresholds are preferred. |
| MAX4617CPE+ | Pin-compatible 16-channel mux but BiCMOS process; 45 Ω RON, higher cost, limited temp range (−40 °C to +85 °C). | Superior RON and bandwidth (100 MHz f−3dB) but lacks extended temperature rating and JEDEC compliance. | Select only when ultra-low RON and high-frequency analog routing (>10 MHz) are mandatory and industrial temp is not required. |
Compared with CD74HC4067M96 and MAX4617CPE+, the 74HCT4067N,112 provides optimal balance of 5 V TTL compatibility, −40 °C to +125 °C operation, and proven JEDEC-standard reliability for industrial control and automotive diagnostics-without requiring layout changes or additional level-shifting components.
Availability
74HCT4067N,112 is available at Aetrix Electronics and suitable for industrial sensor multiplexing, automotive diagnostic interface design, and programmable logic I/O expansion requiring stable component supply and long-term manufacturing continuity.
Supply support for 74HCT4067N,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The 74HCT4067N,112 belongs to NXP's legacy logic portfolio designed for robust, pin-compatible replacements of industry-standard 4000-series and 74-series analog switches-targeting reliability-critical industrial control and automotive subsystems.
FAQ
What is the maximum analog signal voltage range supported by the 74HCT4067N,112?
The 74HCT4067N,112 supports analog signals from GND to VCC, with VCC rated 4.5 V to 5.5 V. Therefore, the absolute maximum analog voltage swing is 0 V to 5.5 V. Exceeding VCC or dropping below GND risks latch-up or damage, and the device is not rated for signals beyond this rail-to-rail range. This makes the 74HCT4067N,112 ideal for 5 V systems like microcontroller-based sensor interfaces.
Does the 74HCT4067N,112 support bidirectional signal flow between Yn and Z terminals?
Yes, the 74HCT4067N,112 implements sixteen fully bidirectional analog switches. Signal flow direction (Yn → Z or Z → Yn) is determined entirely by external circuitry-not by internal design-and propagation delay is symmetric (6 ns typ Z→Yn, 6 ns typ Yn→Z at 5 V). This bidirectionality is intrinsic to the CMOS transmission gate architecture used in the 74HCT4067N,112.
What is the purpose of the 'break-before-make' behavior in the 74HCT4067N,112?
The 'break-before-make' behavior ensures that one channel fully disconnects before the next connects during address transitions (S0–S3 changes). This prevents momentary short-circuits between Yn terminals, which could corrupt sensor readings or damage upstream sources. Verified in the 74HCT4067N,112 datasheet, this feature is essential for fault-tolerant multiplexing in safety-critical applications like engine control units.
Can the 74HCT4067N,112 be used with a 3.3 V microcontroller for address and enable control?
No-the 74HCT4067N,112 is TTL-compatible and specifies VIH ≥ 2.0 V and VIL ≤ 0.8 V at VCC = 4.5–5.5 V. While a 3.3 V GPIO may meet VIL, its VOH (~3.3 V) falls below the minimum VIH (2.0 V) margin required for guaranteed HIGH recognition. Direct interfacing risks metastability. A level shifter or buffer is required to drive S0–S3 and E from 3.3 V logic reliably in the 74HCT4067N,112.
How does the 74HCT4067N,112 handle power supply decoupling for low-noise analog performance?
The 74HCT4067N,112 requires a 100 nF ceramic capacitor placed within 5 mm of pin 24 (VCC) and pin 12 (GND) to suppress high-frequency switching noise that couples into analog paths via substrate or supply rails. This decoupling is critical because the Z terminal's 45 pF capacitance and shared VCC/GND create a noise injection path. Without it, THD increases significantly-verified in the 74HCT4067N,112 characterization data at 1 kHz.
74HCT4067N,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- -
- Multiplexer/Demultiplexer Circuit:
- 16:1
- Number of Circuits:
- 1
- On-State Resistance (Max):
- 120Ohm
- Channel-to-Channel Matching (ΔRon):
- 6Ohm
- Voltage - Supply, Single (V+):
- 4.5V ~ 5.5V
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- 65ns, 60ns
- -3db Bandwidth:
- 100MHz
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 3.5pF
- Current - Leakage (IS(off)) (Max):
- 800nA
- Crosstalk:
- -
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 24-DIP
74HCT4067N,112 FAQ
1.How can I place an order for 74HCT4067N,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT4067N,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT4067N,112 reliable?
The price and inventory of 74HCT4067N,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT4067N,112 is usually 5 days.
3.What payment methods are accepted for 74HCT4067N,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT4067N,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HCT4067N,112?
74HCT4067N,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT4067N,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT4067N,112?
For technical support, including 74HCT4067N,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT4067N,112 requirements.
6.How does Aetrix verify that 74HCT4067N,112 is sourced from the original manufacturer or authorized distributors?
All 74HCT4067N,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT4067N,112 meets industry standards.
7.What is the process for return or replacement of 74HCT4067N,112?
All 74HCT4067N,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT4067N,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT4067N,112 part is unused and in its original packaging.
Return procedure for 74HCT4067N,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HCT4067N,112 Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

