NXP Semiconductors 74HCT423BQ,115
- Part No.:
- 74HCT423BQ,115
- Manufacturer:
- NXP Semiconductors
- Category:
- Multivibrators
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
74HCT423BQ,115.pdf
- Description:
- IC MULTIVIBRATOR 22NS 16DHVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,221
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HCT423BQ,115 from NXP Semiconductors is a dual retriggerable monostable multivibrator with independent reset inputs, designed for precise pulse generation and extension in TTL-compatible digital systems. It features Schmitt-trigger inputs on A/B trigger pins, operates from 4.5 V to 5.5 V, supports −40 °C to +125 °C ambient range, and delivers output pulse widths scalable from nanoseconds to hundreds of microseconds via external REXT/CEXT networks - used in timing control, debounce, and programmable delay circuits.
For engineers reviewing the 74HCT423BQ,115 datasheet, 74HCT423BQ,115 pinout, 74HCT423BQ,115 application, or 74HCT423BQ,115 equivalent, key selection criteria include its dual-channel retriggerability, active-LOW reset behavior, 16-terminal DHVQFN package thermal performance, and guaranteed propagation delays under 77 ns at 5 V - critical for deterministic edge-sensitive timing in industrial control and instrumentation.
Technical Context
The 74HCT423BQ,115 implements two independent monostable multivibrators, each with separate negative-edge (nA) and positive-edge (nB) trigger inputs, direct active-LOW reset (nRD), and complementary outputs (nQ/nQ). Pulse width is set externally via resistor-capacitor networks connected to nREXT/CEXT and nCEXT pins, enabling configurable timing without internal oscillators.
Its HCT logic family ensures TTL-level input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V at VCC = 4.5–5.5 V), while Schmitt-trigger action on nA/nB inputs provides noise immunity against slow-rising signals. The device does not support reset-triggering - unlike the 74HC123/74HCT123 - and relies solely on nA/nB edges and nRD assertion for state control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5 V TTL systems and stable operation across industrial voltage tolerances. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood automotive, motor drives, and high-reliability industrial environments. |
| Propagation Delay | ≤77 ns (nA/nB to nQ/nQ, VCC = 4.5 V) - enables sub-13 MHz timing resolution in synchronous edge-detection applications. |
| Output Drive | ±4 mA at VOL ≤ 0.4 V / VOH ≥ 3.7 V - sufficient to directly drive LED indicators, small-signal logic loads, or CMOS/TTL fan-out without buffering. |
| Input Thresholds | VIH = 2.0 V min, VIL = 0.8 V max - guarantees robust recognition of legacy TTL logic levels and noise margin against ground bounce. |
| Timing Range | Output pulse width scalable from ~75 ns to >450 μs - achieved via REXT = 2–1000 kΩ and CEXT (no upper limit), supporting both fast glitch suppression and long-duration gating. |
| ESD Protection | HBM >2000 V, MM >200 V - meets IEC 61000-4-2 Level 2 requirements for handling and board-level robustness. |
Pinout & Package
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm (SOT763-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 9 (1A, 2A) | Negative-edge trigger input | Triggers monostable on HIGH-to-LOW transition; Schmitt-triggered for noise immunity on slow edges. |
| 2, 10 (1B, 2B) | Positive-edge trigger input | Triggers monostable on LOW-to-HIGH transition; Schmitt-triggered for noise immunity on slow edges. |
| 3, 11 (1RD, 2RD) | Active-LOW direct reset | Forces nQ = LOW / nQ = HIGH immediately and inhibits further triggering until released. |
| 4, 12 (1Q, 2Q) | Active-LOW output | Complementary to nQ; sinks current when asserted; used for inverted logic control or enable signaling. |
| 5, 13 (1Q, 2Q) | Active-HIGH output | Complementary to nQ; sources current when asserted; matches standard active-HIGH interface expectations. |
| 6, 14 (1CEXT, 2CEXT) | External capacitor connection | Connects timing capacitor to GND; recommended to tie externally to GND pin (8) for noise reduction. |
| 7, 15 (1REXT/CEXT, 2REXT/CEXT) | Resistor/capacitor timing node | Connects external timing resistor; inherent pin capacitance is 7 pF - must be included in CEXT calculations. |
| 8 | GND | Ground reference (0 V); all timing and logic thresholds referenced here. |
| 16 | VCC | Positive supply (4.5–5.5 V); powers both monostables and internal logic; decoupling near pin required. |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable operation | Enables indefinite pulse extension by repeated nA/nB edges - supports 100 % duty cycle timing for watchdog timeouts or gated clock stretching. |
| Independent dual channels | Two fully isolated monostables share only VCC/GND; eliminates crosstalk and allows asynchronous timing functions on one die. |
| Schmitt-trigger inputs | Provides ≥0.8 V hysteresis on nA/nB pins - rejects noise on mechanical switch inputs or long PCB traces without external RC filtering. |
| Direct reset control | nRD asserts asynchronously to terminate output pulses and block new triggers - essential for emergency stop or fault-clearing sequences. |
| JEDEC Std. 7A compliance | Guarantees pin compatibility with LSTTL logic families - simplifies drop-in replacement in legacy 74LS423-based designs. |
Applications
| Switch Debounce Circuit | Programmable Pulse Generator |
|---|---|
Use Scenario: Mechanical pushbutton or relay contact closure introduces bounce lasting 1–10 ms, causing false logic transitions in microcontroller inputs. IC Role / Device Role / Timing Role: 74HCT423BQ,115 acts as hardware-based debouncer, generating a clean, fixed-duration output pulse after first valid edge. Use Value: Eliminates need for software polling or timer-based debounce, reducing MCU firmware complexity and ensuring deterministic response within 77 ns of contact closure. | Use Scenario: Industrial PLC requires adjustable ON-time pulses to control solenoid valve dwell duration based on sensor feedback. IC Role / Device Role / Timing Role: 74HCT423BQ,115 serves as retriggerable one-shot, where sensor edge extends pulse width until signal stabilizes. Use Value: Enables analog-like variable pulse width using only digital inputs and passive R/C components - no DAC or microcontroller needed. |
| Watchdog Timer Extension | Glitch Suppression Filter |
Use Scenario: Microcontroller fails to refresh watchdog within timeout window due to transient lockup or ISR overrun. IC Role / Device Role / Timing Role: 74HCT423BQ,115 configured as retriggerable monostable; each WDI pulse resets output, preventing system reset unless pulses cease. Use Value: Provides fail-safe hardware timeout with extendable window up to 450 μs - immune to software glitches that may corrupt internal timers. | Use Scenario: Digital control line experiences sub-100 ns noise spikes from EMI or switching transients, falsely triggering downstream logic. IC Role / Device Role / Timing Role: 74HCT423BQ,115 used as minimum-pulse-width filter; only signals exceeding tW ≥ 75 ns pass through as valid edges. Use Value: Rejects narrow interference while preserving functional signal integrity - achieves hardware-level noise rejection without FPGA or complex filtering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT123DB,118 | SSOP16 package; identical electrical specs but supports reset-triggering (unlike 74HCT423BQ,115). | Enables additional trigger path via nRD; suitable when reset line doubles as event input. | Select when design requires dual-trigger capability (nA/nB + nRD) and SSOP footprint is acceptable. |
| SN74HCT423DR | TSSOP16 package; TI-manufactured; same pinout and function but different thermal resistance (RθJA = 150 K/W vs. NXP's 130 K/W). | Lower power dissipation margin at high ambient; requires tighter thermal layout in dense PCBs. | Select when TI supply chain preference applies and thermal derating is verified per application ambient. |
Compared with 74HCT123DB,118 and SN74HCT423DR, the 74HCT423BQ,115 offers superior thermal performance in DHVQFN packaging and strict non-reset-triggering behavior - ideal for applications requiring predictable, edge-only activation without unintended reset-line interactions.
Availability
74HCT423BQ,115 is available at Aetrix Electronics and suitable for industrial control systems, automotive body electronics, test equipment timing modules, and embedded instrumentation requiring stable component supply across extended temperature ranges.
Supply support for 74HCT423BQ,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The 74HCT423BQ,115 belongs to NXP's legacy HC/HCT logic family, engineered for pin-compatible migration from bipolar TTL while delivering CMOS power efficiency and noise immunity - targeting cost-sensitive, high-volume timing and interface applications.
FAQ
What is the minimum output pulse width achievable with the 74HCT423BQ,115?
The 74HCT423BQ,115 achieves a minimum output pulse width of 75 ns when configured with REXT = 5 kΩ and CEXT = 0 pF at VCC = 5.0 V. This value is measured from nA/nB trigger to nQ/nQ transition and reflects the device's intrinsic propagation and transition delays - independent of external timing components.
Can the 74HCT423BQ,115 be triggered through its reset pin (nRD)?
No, the 74HCT423BQ,115 cannot be triggered via the nRD pin. Unlike the 74HCT123, this device uses nRD exclusively for asynchronous reset - forcing nQ LOW and nQ HIGH while inhibiting all triggering. Triggering occurs only on nA (negative edge) or nB (positive edge) inputs, as confirmed in the functional description and Figure 10 of the NXP datasheet Rev. 6.
What are the recommended external timing component values for a 100 μs pulse width using the 74HCT423BQ,115?
For a nominal 100 μs output pulse width at VCC = 5.0 V, use REXT = 22 kΩ and CEXT = 4.5 nF. This follows the formula tW = 0.45 × REXT × CEXT (with REXT in kΩ and CEXT in nF), yielding 100 μs. Include the 7 pF inherent pin capacitance at nREXT/CEXT in final CEXT selection.
Does the 74HCT423BQ,115 require external pull-up or pull-down resistors on its inputs?
No, the 74HCT423BQ,115 does not require external pull-up or pull-down resistors on nA, nB, or nRD inputs. Its TTL-compatible input thresholds and Schmitt-trigger action on nA/nB ensure stable logic levels even with floating or high-impedance sources. However, unused inputs should be tied to VCC or GND to prevent noise coupling.
How does the DHVQFN16 package of the 74HCT423BQ,115 improve thermal performance compared to SO16?
The DHVQFN16 package (SOT763-1) of the 74HCT423BQ,115 provides lower thermal resistance than SO16: total power dissipation remains rated at 500 mW up to +60 °C before linear derating begins (4.5 mW/K), whereas SO16 derates from +70 °C at 8 mW/K. This enables higher sustained power operation in compact, thermally constrained layouts typical in modern industrial modules.
74HCT423BQ,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HCT
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 22 ns
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 4.5 V ~ 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-DHVQFN (2.5x3.5)
74HCT423BQ,115 FAQ
1.How can I place an order for 74HCT423BQ,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HCT423BQ,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HCT423BQ,115 reliable?
The price and inventory of 74HCT423BQ,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT423BQ,115 is usually 5 days.
3.What payment methods are accepted for 74HCT423BQ,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HCT423BQ,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HCT423BQ,115?
74HCT423BQ,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HCT423BQ,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HCT423BQ,115?
For technical support, including 74HCT423BQ,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT423BQ,115 requirements.
6.How does Aetrix verify that 74HCT423BQ,115 is sourced from the original manufacturer or authorized distributors?
All 74HCT423BQ,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT423BQ,115 meets industry standards.
7.What is the process for return or replacement of 74HCT423BQ,115?
All 74HCT423BQ,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT423BQ,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT423BQ,115 part is unused and in its original packaging.
Return procedure for 74HCT423BQ,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HCT423BQ,115 Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

