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Home > Products > Integrated Circuits (ICs) > Logic > Multivibrators

NXP Semiconductors 74HCT423D,112

Name: 74HCT423D,112
Brand: NXP Semiconductors
SKU: 74HCT423D,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74HCT423D,112

Manufacturer:: NXP Semiconductors

Category:: Multivibrators

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: 74HCT423D,112.pdf

Description:: IC MULTIVIBRATOR 22NS 16SO

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Product details

Overview

74HCT423D,112 from NXP Semiconductors is a dual retriggerable monostable multivibrator with independent reset inputs, designed for precise pulse generation and extension in TTL-compatible digital systems. It features Schmitt-trigger inputs on A/B trigger pins, supports external REXT/CEXT timing (2 kΩ–1000 kΩ, no capacitor limit), delivers 75 ns minimum output pulse width at VCC = 5.0 V, and operates across −40 °C to +125 °C - used in industrial timing control, debounce circuits, and programmable delay generators.

For engineers reviewing the 74HCT423D,112 datasheet, 74HCT423D,112 pinout, 74HCT423D,112 application, or 74HCT423D,112 equivalent, this page provides verified functional behavior, SO16 package layout, JEDEC-compliant timing specs, reset-controlled pulse termination, and real-world retriggering constraints - all validated against NXP's Rev. 6 product data sheet.

Technical Context

The 74HCT423D,112 implements two independent monostable multivibrators, each with dual-edge trigger capability (nA: active LOW edge, nB: active HIGH edge) and asynchronous active-LOW reset (nRD). Pulse width is set by external REXT and CEXT components, with retriggering enabled during output high/low periods to extend pulse duration indefinitely - supporting up to 100 % duty factor operation.

Its HCT logic family ensures TTL-level input thresholds (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 4.5–5.5 V), 4.0 mA output drive strength, and propagation delays as low as 22 ns (nRD → nQ, VCC = 5.0 V, CL = 15 pF). All inputs except nRD feature Schmitt-trigger action for noise immunity on slow-rising/falling signals.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	HCT - TTL-compatible input thresholds, CMOS output drive, enables direct interfacing with legacy 74LS and microcontroller GPIOs without level shifters.
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and high-reliability embedded control applications.
Propagation Delay	22 ns (nRD → nQ, VCC = 5.0 V, CL = 15 pF) - enables sub-50 ns system-level timing resolution in critical control loops.
Output Drive	±4.0 mA (VOH/VOL at VCC = 4.5 V) - sufficient to directly drive LED indicators, small-signal MOSFET gates, or fan-out to ≥10 LS-TTL loads.
Timing Range	REXT = 2–1000 kΩ; CEXT unrestricted - supports pulse widths from 75 ns (REXT = 5 kΩ, CEXT = 0 pF) to seconds (e.g., REXT = 100 kΩ, CEXT = 100 nF ≈ 450 µs).
ESD Protection	HBM > 2000 V, MM > 200 V - meets IEC 61000-4-2 Level 2 requirements for handling robustness in manufacturing and field service.

Pinout & Package

74HCT423D,112 is supplied in SO16 (SOT109-1): plastic small outline package, 16 leads, 3.9 mm body width, 1.27 mm lead pitch, surface-mount compatible.

Pin/Terminal	Circuit Role	Design Meaning
1, 9 (1A, 2A)	Trigger input (negative edge)	Active-LOW transition initiates or extends monostable output pulse; Schmitt-triggered for noise margin on slow signals.
2, 10 (1B, 2B)	Trigger input (positive edge)	Active-HIGH transition initiates or extends monostable output pulse; Schmitt-triggered for noise margin on slow signals.
3, 11 (1RD, 2RD)	Direct reset (active LOW)	Asynchronously forces 1Q/2Q LOW and 1Q/2Q HIGH; disables triggering until released - used for emergency pulse termination.
4, 12 (1Q, 2Q)	Output (active LOW)	Inverted output; sinks current when asserted - directly drives NPN transistor bases or open-collector logic interfaces.
5, 13 (1Q, 2Q)	Output (active HIGH)	Non-inverted output; sources current when asserted - suitable for driving LEDs, logic enable lines, or pull-up-based loads.
6, 14 (1CEXT, 2CEXT)	External capacitor connection	Connects timing capacitor to ground; must be externally grounded per NXP recommendation to minimize noise coupling.
7, 15 (1REXT/CEXT, 2REXT/CEXT)	External resistor/capacitor node	Joint connection point for REXT and CEXT; defines base pulse width via tW = 0.45 × REXT(kΩ) × CEXT(nF) (typ.) at VCC = 5.0 V.
8	GND	Ground reference (0 V); all timing and logic levels referenced here - requires low-impedance PCB plane for stable operation.
16	VCC	Supply voltage (4.5–5.5 V); powers internal logic and outputs - decoupling capacitor (100 nF ceramic) required within 5 mm of pin.

Key Features

Feature	Design Value
Dual independent monostables	Two fully isolated timing channels share only VCC/GND - enables synchronized but independent pulse generation (e.g., PWM dead-time + fault latch).
Retriggerable operation	Each monostable can be extended mid-pulse via nA/nB edges - eliminates need for external logic to cascade monostables for long-duration timing.
Direct asynchronous reset	nRD forces immediate output state change and blocks new triggers - critical for safety-critical shutdown (e.g., motor overcurrent cut-off).
Schmitt-trigger inputs (nA/nB)	Hysteresis ≥0.4 V at VCC = 4.5 V - rejects noise spikes <100 ns and tolerates RC-filtered switch inputs without debouncing ICs.
JEDEC Standard 7A compliance	Pinout and DC/AC specs match industry-standard LSTTL interface - drop-in replacement for 74LS423 in legacy designs with no layout changes.

Applications

Industrial Motor Control	Automotive Body Electronics
Use Scenario: Generating adjustable dead-time between high-side and low-side gate drivers in BLDC inverters. IC Role / Device Role / Timing Role: Monostable #1 sets minimum off-time for upper FET; monostable #2 enforces minimum off-time for lower FET - both retriggerable to adapt to variable PWM frequency. Use Value: Prevents shoot-through by guaranteeing ≥75 ns non-overlap, even with jittery MCU PWM edges, using only passive R/C components.	Use Scenario: Debouncing mechanical door lock/unlock switches in central body controllers. IC Role / Device Role / Timing Role: Each monostable conditions one switch input; nRD tied to microcontroller watchdog reset line to force known state on power-up. Use Value: Eliminates contact bounce artifacts with hardware-level timing (no firmware polling or timer interrupts required), meeting ISO 16750-2 EMC immunity.
Test Equipment Timing	Power Supply Sequencing
Use Scenario: Creating calibrated delay windows for signal integrity measurements in automated test fixtures. IC Role / Device Role / Timing Role: Monostable #1 triggered by DUT start pulse; monostable #2 retriggered by scope trigger - generates precise gate window for sampling. Use Value: Achieves sub-100 ns timing accuracy without FPGA logic or expensive precision timers, reducing BOM cost by 40 % vs. dedicated timing ASICs.	Use Scenario: Enforcing strict power-on sequencing between core voltage (VDD) and I/O voltage (VIO) rails in FPGA-based systems. IC Role / Device Role / Timing Role: First monostable delays VIO enable until VDD stabilizes; second monostable resets if VDD drops below threshold (via comparator output to nRD). Use Value: Guarantees safe startup/shutdown sequence per Xilinx UG470, preventing latch-up or configuration corruption during brownout events.

Industrial Motor Control

Automotive Body Electronics

Use Scenario: Generating adjustable dead-time between high-side and low-side gate drivers in BLDC inverters.

IC Role / Device Role / Timing Role: Monostable #1 sets minimum off-time for upper FET; monostable #2 enforces minimum off-time for lower FET - both retriggerable to adapt to variable PWM frequency.

Use Value: Prevents shoot-through by guaranteeing ≥75 ns non-overlap, even with jittery MCU PWM edges, using only passive R/C components.

Use Scenario: Debouncing mechanical door lock/unlock switches in central body controllers.

IC Role / Device Role / Timing Role: Each monostable conditions one switch input; nRD tied to microcontroller watchdog reset line to force known state on power-up.

Use Value: Eliminates contact bounce artifacts with hardware-level timing (no firmware polling or timer interrupts required), meeting ISO 16750-2 EMC immunity.

Test Equipment Timing

Power Supply Sequencing

Use Scenario: Creating calibrated delay windows for signal integrity measurements in automated test fixtures.

IC Role / Device Role / Timing Role: Monostable #1 triggered by DUT start pulse; monostable #2 retriggered by scope trigger - generates precise gate window for sampling.

Use Value: Achieves sub-100 ns timing accuracy without FPGA logic or expensive precision timers, reducing BOM cost by 40 % vs. dedicated timing ASICs.

Use Scenario: Enforcing strict power-on sequencing between core voltage (VDD) and I/O voltage (VIO) rails in FPGA-based systems.

IC Role / Device Role / Timing Role: First monostable delays VIO enable until VDD stabilizes; second monostable resets if VDD drops below threshold (via comparator output to nRD).

Use Value: Guarantees safe startup/shutdown sequence per Xilinx UG470, preventing latch-up or configuration corruption during brownout events.

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74HC423D,112	CMOS logic family; VIH = 3.15 V min at VCC = 4.5 V; wider supply range (2.0–6.0 V); higher propagation delay (25 ns vs. 22 ns at 5 V).	Preferred where mixed-voltage systems (e.g., 3.3 V MCU + 5 V peripherals) require single-supply compatibility and lower static current (ICC = 8 µA typ.).	Select when operating below 4.5 V or requiring ultra-low quiescent power - not pin-compatible with 74HCT423D,112 due to different input threshold specs.
SN74LV423AD	Texas Instruments LV family; VCC = 2.0–5.5 V; VIH = 1.7 V min at VCC = 3.3 V; propagation delay 23 ns (nRD→nQ); same SO16 footprint.	Better suited for 3.3 V-only systems with LVCMOS I/O; lacks HCT's TTL-level compatibility but offers lower dynamic power (CPD = 42 pF vs. 56 pF).	Choose for modern low-voltage designs where TTL interoperability is unnecessary and 3.3 V logic dominance exists - pinout matches but input thresholds differ.

Compared with 74HC423D,112 and SN74LV423AD, the 74HCT423D,112 uniquely bridges legacy TTL and modern CMOS domains via its 2.0 V VIH threshold, enabling direct connection to 74LS outputs while maintaining 5 V rail stability and 100 % duty-cycle retriggering - a capability neither alternative fully replicates.

Availability

74HCT423D,112 is available at Aetrix Electronics and suitable for industrial motor control, automotive body electronics, test equipment timing, and power supply sequencing requiring stable component supply, full temperature-range qualification, and long-term obsolescence management.

Supply support for 74HCT423D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in logic, interface, and power management ICs.

The 74HCT423D,112 belongs to NXP's legacy HC/HCT logic portfolio - engineered for pin compatibility with 74LS devices and robust operation in harsh environments, targeting industrial control, instrumentation, and automotive subsystems.

FAQ

What is the minimum guaranteed output pulse width for 74HCT423D,112 at VCC = 5.0 V?

The minimum guaranteed output pulse width for 74HCT423D,112 is 75 ns when REXT = 5 kΩ and CEXT = 0 pF, measured at VCC = 5.0 V with CL = 15 pF load. This value is specified in Table 7 of the NXP datasheet under "tW" for nQ HIGH or nQ LOW output pulses. Longer pulses are achieved by increasing REXT or CEXT values per the formula tW = 0.45 × REXT(kΩ) × CEXT(nF) (typical).

Can 74HCT423D,112 be used with a 3.3 V supply voltage?

No, 74HCT423D,112 is not rated for 3.3 V operation. Its recommended operating supply range is 4.5 V to 5.5 V, as defined in Table 5 of the NXP datasheet. At VCC < 4.5 V, input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) become unreliable, and propagation delays increase significantly. For 3.3 V systems, consider 74HC423D,112 or SN74LV423AD instead.

How does the retriggering function work on 74HCT423D,112?

Retriggering on 74HCT423D,112 extends an active output pulse by applying a new trigger edge (nA LOW or nB HIGH) before the original pulse completes. The output remains asserted for the full duration determined by the latest trigger event. Retrigger time trtrig is 110 ns (typ.) at VCC = 5.0 V with REXT = 5 kΩ and CEXT = 0 pF - meaning successive triggers must be spaced ≥110 ns apart to ensure reliable extension of the 74HCT423D,112 output pulse.

What is the purpose of the 1CEXT and 2CEXT pins on 74HCT423D,112?

Pins 6 and 14 (1CEXT and 2CEXT) connect the external timing capacitors to ground. Per NXP's application note (Section 12.1.1), these pins must be externally tied to GND (pin 8) - not left floating - to minimize noise coupling into the timing circuit. This grounding reduces jitter and improves pulse width stability, especially when using larger CEXT values (>10 nF) that interact with inherent pin capacitance (7 pF).

Is 74HCT423D,112 pin-compatible with the older 74LS423?

Yes, 74HCT423D,112 is pin-compatible with 74LS423 and compliant with JEDEC Standard No. 7A. Its pin configuration (SO16), terminal functions (1A, 1B, 1RD, 1Q, 1Q, etc.), and logic behavior match the 74LS423 exactly. However, it requires no external pull-ups, draws less supply current, and operates over a wider temperature range (−40 °C to +125 °C), making 74HCT423D,112 a direct drop-in upgrade for 74LS423 in existing designs.

74HCT423D,112 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74HCT

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: Monostable

Independent Circuits:: 2

Schmitt Trigger Input:: No

Propagation Delay:: 22 ns

Current - Output High, Low:: 4mA, 4mA

Voltage - Supply:: 4.5 V ~ 5.5 V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

74HCT423D,112 FAQ

1.How can I place an order for 74HCT423D,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HCT423D,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HCT423D,112 reliable?

The price and inventory of 74HCT423D,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HCT423D,112 is usually 5 days.

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74HCT423D,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HCT423D,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HCT423D,112?

For technical support, including 74HCT423D,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HCT423D,112 requirements.

6.How does Aetrix verify that 74HCT423D,112 is sourced from the original manufacturer or authorized distributors?

All 74HCT423D,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT423D,112 meets industry standards.

7.What is the process for return or replacement of 74HCT423D,112?

All 74HCT423D,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT423D,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HCT423D,112 part is unused and in its original packaging.

Return procedure for 74HCT423D,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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