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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

NXP Semiconductors 74HCT7046AD,118

Name: 74HCT7046AD,118
Brand: NXP Semiconductors
SKU: 74HCT7046AD,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74HCT7046AD,118

Manufacturer:: NXP Semiconductors

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: 74HCT7046AD,118.pdf

Description:: IC PHASE LOCK LOOP 16SO

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74HCT7046AD,118 from NXP Semiconductors is a high-speed CMOS phase-locked-loop (PLL) IC with integrated lock detector, dual phase comparators (XOR and edge-triggered JK), linear VCO (centre frequency up to 17 MHz at V_CC = 4.5 V), and VCO-inhibit control. It operates across 4.5–5.5 V for digital logic and 3.0–6.0 V for VCO section, enabling FM demodulation, frequency synthesis, and motor-speed control in industrial timing systems.

For engineers reviewing the 74HCT7046AD,118 datasheet, 74HCT7046AD,118 pinout, 74HCT7046AD,118 application, or 74HCT7046AD,118 equivalent, key selection criteria include VCO linearity (≤0.4% at V_CC = 4.5 V), lock detector output (active HIGH on pin 1), dual comparator selection flexibility, and HCT-level TTL-compatible inputs - all critical for stable PLL loop design in noise-sensitive communication and control circuits.

Technical Context

The 74HCT7046AD,118 integrates a linear voltage-controlled oscillator (VCO) with op-amp buffering for zero voltage offset, two independent phase comparators (PC1: XOR; PC2: edge-triggered JK flip-flop), and a dedicated lock detector (LD) output. Its VCO requires external R1/R2 and C1 components to set centre frequency (f_o) and offset, with DEMOUT (pin 10) providing buffered replica of VCOIN voltage for low-pass filter decoupling.

PC1 delivers maximum lock range with 50% duty-cycle inputs and exhibits ripple at 2f_i, while PC2 enables frequency/phase detection independent of duty factor, offers 3-state output, and achieves equal capture/lock ranges. The inhibit input (INH, pin 5) disables both VCO and demodulator to reduce standby current, and CLD capacitor (pin 15 to GND) sets lock detector response time.

Key Specifications

Parameter	Value and Actual Design Meaning
VCO centre frequency (f_o)	11.0–17.0 MHz at V_CC = 4.5 V, R1 = 3 kΩ, C1 = 40 pF - defines PLL operating band for FM demodulation or tone decoding
VCO frequency linearity	≤0.4% (typ.) - ensures precise voltage-to-frequency conversion and minimal distortion in motor-speed feedback loops
Phase comparator gain (K_p)	0.159 V/° (PC1), 0.0796 V/° (PC2) - determines loop gain stability and lock acquisition speed
Lock detector output (LD)	Active HIGH (pin 1) - provides unambiguous system-level lock status without external logic
Input compatibility	TTL-level (V_IH = 2.0 V, V_IL = 0.8 V at V_CC = 4.5 V) - enables direct interfacing with legacy microcontrollers and logic families
Supply voltage range	Digital section: 4.5–5.5 V; VCO section: 3.0–6.0 V - supports mixed-supply designs with separate analog/digital rails
Quiescent supply current	8.0–160 µA (VCO disabled) - enables low-power standby in battery-operated synchronization circuits

Pinout & Package

74HCT7046AD,118 is housed in a 16-pin SO16 (Small Outline) plastic package per JEDEC MS-012, with 1.27 mm pitch and standard surface-mount footprint.

Pin/Terminal	Circuit Role	Design Meaning
1 (LD)	Lock detector output	Open-drain compatible HIGH when PLL is locked - used for status monitoring or automatic frequency switching
2 (PC1OUT)	Phase comparator 1 output	XOR-based error signal - feeds low-pass filter to VCOIN; requires external RC filtering for stable loop dynamics
3 (COMPIN)	Comparator input	Reference signal input for phase comparison - accepts DC-coupled or AC-coupled signals with self-biasing
4 (VCOOUT)	VCO output	50% duty-cycle square wave (±1%) - directly drives COMPIN or external frequency dividers for multiplication
5 (INH)	Inhibit control input	Active HIGH disables VCO and DEMOUT - reduces standby power and enables ON/OFF keying
6,7 (C1A, C1B)	VCO capacitor terminals	Connect external timing capacitor C1 (≥40 pF) - sets VCO frequency range and temperature stability
8 (GND)	Ground reference	Common return for digital and VCO sections - must be low-impedance to minimize phase noise
9 (VCOIN)	VCO control input	Analog voltage (1.1–3.4 V) controlling oscillation frequency - buffered by internal op-amp to prevent loading
10 (DEMOUT)	Demodulator output	Exact replica of VCOIN voltage - allows remote low-pass filtering without signal degradation
11,12 (R1, R2)	VCO resistor terminals	Set centre frequency (R1) and optional offset (R2) - parallel R1\|\|R2 > 2.7 kΩ required for stability
13 (PC2OUT)	Phase comparator 2 output	3-state up/down error signal - eliminates ripple at lock point and improves noise immunity over PC1
14 (SIGIN)	Signal input	Primary input for PLL reference - self-biased for small-swing signals; large-swing signals may be DC-coupled
15 (CLD)	Lock detector capacitor	Connects to GND via capacitor C_LD - sets lock detection time constant per Fig.32 in datasheet
16 (V_CC)	Positive supply	4.5–5.5 V for TTL-compatible logic - powers digital comparators, lock detector, and output drivers

Key Features

Feature	Design Value
Dual selectable phase comparators	PC1 (XOR) for high-noise-rejection applications; PC2 (edge-triggered JK) for duty-cycle-insensitive frequency locking
VCO-inhibit control	Pin 5 (INH) disables VCO and DEMOUT to reduce standby current - essential for power-gated systems
Linear VCO with op-amp buffering	Zero voltage offset and ≤0.4% linearity - enables accurate voltage-to-frequency conversion and stable servo control
Lock detector with external timing	Pin 1 (LD) outputs active-HIGH lock status; CLD capacitor (pin 15–GND) sets response time per design requirements
Demodulator output (DEMOUT)	Pin 10 replicates VCOIN voltage exactly - eliminates threshold drop seen in conventional demodulators for precision filtering
HCT-level TTL-compatible inputs	VIH = 2.0 V, VIL = 0.8 V at VCC = 4.5 V - ensures interoperability with 5 V microcontrollers and legacy logic without level shifters

Applications

FM Demodulation	Frequency Synthesis
Use Scenario: Recovering audio from broadcast FM signals in consumer receivers or test equipment. IC Role / Device Role / Timing Role: PLL acts as synchronous demodulator - VCO tracks carrier frequency, PC2 compares phase/frequency, DEMOUT extracts baseband. Use Value: Achieves <1% THD due to VCO linearity and low DEMOUT offset (±20 mV), outperforming passive discriminators in SNR-limited environments.	Use Scenario: Generating stable, programmable clock frequencies from a single crystal reference in communication transceivers. IC Role / Device Role / Timing Role: PLL functions as frequency multiplier - SIGIN = reference clock, VCOOUT = multiplied output, PC1 locks loop to integer multiple. Use Value: Supports 11–17 MHz output with ±0.15%/K tempco, enabling jitter-tolerant local oscillator generation without external synthesizer ICs.
Tone Decoding	Motor-Speed Control
Use Scenario: Detecting DTMF or sub-audible tones in security systems or industrial telemetry. IC Role / Device Role / Timing Role: PLL serves as narrowband tracking filter - lock detector (LD) asserts when input matches pre-set VCO centre frequency. Use Value: Lock detection window defined by f_L (up to ±8.5 MHz) enables selective tone recognition with minimal false triggers under amplitude modulation.	Use Scenario: Regulating DC motor RPM using feedback from tachometer pulses in industrial actuators. IC Role / Device Role / Timing Role: PLL converts tachometer pulse frequency to proportional analog voltage (VCOIN) - fed to motor driver as speed command. Use Value: VCO linearity ≤0.4% ensures <0.5% speed regulation error across 10:1 RPM range, critical for precision motion control.

FM Demodulation

Frequency Synthesis

Use Scenario: Recovering audio from broadcast FM signals in consumer receivers or test equipment.

IC Role / Device Role / Timing Role: PLL acts as synchronous demodulator - VCO tracks carrier frequency, PC2 compares phase/frequency, DEMOUT extracts baseband.

Use Value: Achieves <1% THD due to VCO linearity and low DEMOUT offset (±20 mV), outperforming passive discriminators in SNR-limited environments.

Use Scenario: Generating stable, programmable clock frequencies from a single crystal reference in communication transceivers.

IC Role / Device Role / Timing Role: PLL functions as frequency multiplier - SIGIN = reference clock, VCOOUT = multiplied output, PC1 locks loop to integer multiple.

Use Value: Supports 11–17 MHz output with ±0.15%/K tempco, enabling jitter-tolerant local oscillator generation without external synthesizer ICs.

Tone Decoding

Motor-Speed Control

Use Scenario: Detecting DTMF or sub-audible tones in security systems or industrial telemetry.

IC Role / Device Role / Timing Role: PLL serves as narrowband tracking filter - lock detector (LD) asserts when input matches pre-set VCO centre frequency.

Use Value: Lock detection window defined by f_L (up to ±8.5 MHz) enables selective tone recognition with minimal false triggers under amplitude modulation.

Use Scenario: Regulating DC motor RPM using feedback from tachometer pulses in industrial actuators.

IC Role / Device Role / Timing Role: PLL converts tachometer pulse frequency to proportional analog voltage (VCOIN) - fed to motor driver as speed command.

Use Value: VCO linearity ≤0.4% ensures <0.5% speed regulation error across 10:1 RPM range, critical for precision motion control.

Equivalent & Alternatives

The following parts are listed as comparable options for similar phase-locked-loop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
CD4046BE	CMOS-only (no TTL compatibility); VCO f_o max = 1.2 MHz at 5 V; no DEMOUT pin; single-phase comparator (XOR only)	Limited to low-frequency (<1 MHz) applications; lacks PC2 for frequency-locking; no buffered demodulator output	Select when cost sensitivity outweighs performance - suitable for basic tone generators or educational kits where speed and linearity are secondary.
SN74LV4046A	Lower-voltage operation (1.65–5.5 V); higher f_o (20 MHz typ.); improved VCO linearity (0.25%); no CLD pin - integrated lock detection	Better suited for modern low-voltage MCU interfaces; tighter linearity benefits precision V/F conversion; simplified lock detection	Prefer for new designs targeting 3.3 V systems or requiring >17 MHz operation - but requires PCB layout changes due to different pinout and absence of CLD terminal.

Compared with CD4046BE and SN74LV4046A, the 74HCT7046AD,118 uniquely balances TTL compatibility, dual-comparator flexibility, and buffered DEMOUT - making it optimal for industrial upgrades where legacy 5 V logic coexists with analog control loops requiring precise VCO linearity and external filter design freedom.

Availability

74HCT7046AD,118 is available at Aetrix Electronics and suitable for FM demodulation, frequency synthesis, and motor-speed control applications requiring stable component supply, long-term industrial lifecycle support, and guaranteed traceable sourcing.

Supply support for 74HCT7046AD,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips' pioneering logic IC development.

The 74HCT7046AD,118 belongs to NXP's legacy 74HCT logic family, designed specifically for robust 5 V mixed-signal systems requiring TTL-compatible inputs, low-power analog integration, and reliable PLL functionality in harsh industrial environments.

FAQ

What is the maximum VCO centre frequency achievable with 74HCT7046AD,118?

The 74HCT7046AD,118 achieves a typical VCO centre frequency (f_o) of 17 MHz at V_CC = 4.5 V, R1 = 3 kΩ, and C1 = 40 pF. This value is confirmed in the AC Characteristics table (page 19) under "fo" for 74HCT at +25 °C. Operation beyond 17 MHz is not specified and may compromise linearity or lock range.

How does the DEMOUT pin (pin 10) function in 74HCT7046AD,118?

The DEMOUT pin of the 74HCT7046AD,118 provides an exact buffered replica of the VCOIN voltage - unlike conventional demodulators, it exhibits no threshold voltage drop. This allows designers to place the low-pass filter remotely without signal degradation, improving loop stability in noise-prone layouts.

Can 74HCT7046AD,118 operate with separate supplies for digital and VCO sections?

Yes - the 74HCT7046AD,118 supports independent supply domains: the digital section (comparators, lock detector) operates from 4.5–5.5 V, while the VCO section functions from 3.0–6.0 V. This enables optimized noise isolation in mixed-signal PCBs, provided ground paths remain common and low-impedance.

What is the purpose of the CLD pin (pin 15) on 74HCT7046AD,118?

The CLD pin on the 74HCT7046AD,118 connects to GND via an external capacitor (C_LD) to set the lock detector's response time. Its value is determined using Figure 32 in the datasheet and directly affects how quickly the LD output (pin 1) asserts after lock acquisition or releases during loss-of-lock events.

Which phase comparator should I use for frequency discrimination in 74HCT7046AD,118?

For frequency discrimination, PC2 (edge-triggered JK flip-flop) is preferred in the 74HCT7046AD,118 because it locks independently of input duty cycle, provides 3-state output to minimize ripple, and delivers equal capture and lock ranges - ensuring reliable detection even with distorted or asymmetrical input waveforms.

74HCT7046AD,118 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74HCT

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Phase Lock Loop (PLL)

PLL:: Yes

Input:: Clock

Output:: Clock

Number of Circuits:: 1

Ratio - Input:Output:: 2:3

Differential - Input:Output:: No/No

Frequency - Max:: 21MHz

Divider/Multiplier:: No/No

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-SO

74HCT7046AD,118 FAQ

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Please submit a Request for Quotation (RFQ) for 74HCT7046AD,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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6.How does Aetrix verify that 74HCT7046AD,118 is sourced from the original manufacturer or authorized distributors?

All 74HCT7046AD,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HCT7046AD,118 meets industry standards.

7.What is the process for return or replacement of 74HCT7046AD,118?

All 74HCT7046AD,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HCT7046AD,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HCT7046AD,118 part is unused and in its original packaging.

Return procedure for 74HCT7046AD,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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