NXP Semiconductors 74HCT7046AN,112
- Part No.:
- 74HCT7046AN,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
74HCT7046AN,112.pdf
- Description:
- IC PHASE LOCK LOOP 16DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74HCT7046AN,112 from NXP Semiconductors (formerly Philips) is a high-speed CMOS phase-locked-loop IC with integrated lock detector, dual phase comparators (XOR and edge-triggered JK), linear VCO, and demodulator output. It delivers 17 MHz typical center frequency at 4.5 V, 50% VCO duty factor, and ±20 mV demodulator offset - used in FM demodulation, frequency synthesis, and tone decoding circuits.
For engineers reviewing the 74HCT7046AN,112 datasheet, 74HCT7046AN,112 pinout, 74HCT7046AN,112 application, or 74HCT7046AN,112 equivalent, key selection criteria include VCO linearity (0.4%), temperature stability (0.15%/K), dual comparator architecture, inhibit-controlled standby power, and compatibility with passive second-order loop filters.
Technical Context
The 74HCT7046AN,112 integrates a linear op-amp-based voltage-controlled oscillator (VCO) with external R1/R2/C1 tuning, two independent phase comparators sharing a common signal amplifier, and a dedicated lock detector output (LD) referenced to CLD capacitor. Its VCO input (pin 9) drives a buffered demodulator output (DEMOUT, pin 10) matching the VCO input voltage level - eliminating threshold drop artifacts found in legacy PLLs.
Phase comparator 1 (PC1, XOR) requires 50% duty-cycle inputs and provides π-radian phase gain; PC2 (edge-triggered JK flip-flop) supports arbitrary duty cycles, delivers 4π-radian phase gain, enables true frequency/phase detection, and achieves zero steady-state phase error across the full VCO range - with 3-state output reducing low-pass filter power dissipation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO center frequency | 17 MHz typical at VCC = 4.5 V, R1 = 3 kΩ, C1 = 40 pF - sets base tuning range for synthesis and demodulation |
| VCO frequency linearity | 0.4% max deviation - ensures accurate voltage-to-frequency conversion and stable FM modulation |
| Frequency stability vs temp | 0.15%/K - enables reliable operation across −40 °C to +125 °C industrial ambient range |
| Duty factor (VCOOUT) | 50% ±1% - guarantees precise timing reference for downstream logic and dividers |
| Demodulator offset (VCOIN→DEMOUT) | ±20 mV - minimizes DC error in analog PLL feedback paths and lock detection thresholds |
| Input sensitivity (AC-coupled) | 15 mVp-p at 1 MHz - supports low-amplitude signal conditioning without pre-amplification |
| Propagation delay (SIGIN→PC1OUT) | 21–60 ns - defines minimum loop response time and capture bandwidth in closed-loop designs |
Pinout & Package
74HCT7046AN,112 is supplied in a 16-pin plastic DIP (dual in-line package) with 0.3-inch body width and standard through-hole mounting. Pin spacing follows JEDEC MS-001AA outline.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (LD) | Lock detector output | Active-HIGH signal indicating PLL lock state; requires external CLD capacitor (pin 15 to GND) for hysteresis |
| 2 (PC1OUT) | Phase comparator 1 output | XOR gate output feeding low-pass filter; average voltage proportional to phase difference (VCC/π × Δφ) |
| 3 (COMPIN) | Comparator input | Reference input for both PC1 and PC2; accepts DC- or AC-coupled signals with self-biasing |
| 4 (VCOOUT) | VCO output | 50%-duty square wave output; can drive COMPIN directly or via frequency divider |
| 5 (INH) | Inhibit control | Active-HIGH digital enable/disable for VCO and demodulator - reduces standby current to <160 µA |
| 6,7 (C1A,C1B) | VCO capacitor terminals | Connect external timing capacitor C1 (≥40 pF); differential connection improves noise immunity |
| 8 (GND) | Ground reference | Common return for digital, VCO, and demodulator sections; decoupling critical for lock stability |
| 9 (VCOIN) | VCO input control | Analog voltage input (1.1–3.4 V) setting instantaneous VCO frequency; buffered by op-amp |
| 10 (DEMOUT) | Demodulator output | Buffered replica of VCOIN voltage - eliminates threshold drop for accurate loop filtering |
| 11,12 (R1,R2) | VCO resistor terminals | External resistors setting VCO bias current; R1 sets center frequency, R2 adds frequency offset |
| 13 (PC2OUT) | Phase comparator 2 output | 3-state up/down output enabling zero-phase-error tracking and reduced filter power |
| 14 (SIGIN) | Signal input | Primary input for PLL reference signal; self-biased for small-swing AC coupling or direct DC coupling |
| 15 (CLD) | Lock detector capacitor | Connection point for external capacitor to ground; sets lock detector response time and hysteresis |
| 16 (VCC) | Positive supply | 4.5–5.5 V digital/VCO supply; VCO section operates down to 3.0 V, digital section to 2.0 V |
Key Features
| Feature | Design Value |
|---|---|
| Dual selectable phase comparators | XOR (PC1) for high-noise rejection and harmonic locking; edge-triggered JK (PC2) for zero-phase-error frequency tracking and wide capture range |
| VCO-inhibit control | Active-HIGH INH pin disables VCO and demodulator, reducing quiescent ICC to ≤160 µA - ideal for battery-powered tone decoders |
| Linear op-amp VCO architecture | Eliminates exponential VCO nonlinearity; achieves 0.4% frequency linearity over full control voltage range |
| Matched DEMOUT voltage | DEMOUT (pin 10) equals VCOIN voltage - removes 0.7 V diode drop error in traditional emitter-follower buffers |
| Self-biasing SIGIN/COMPIN inputs | Internal bias network maintains small-swing AC signals in linear region without external DC restoration |
| Lock detector with external CLD | LD (pin 1) asserts HIGH when PLL locked; CLD capacitor (pin 15–GND) sets hysteresis to prevent false unlock during transients |
Applications
| FM Demodulation | Frequency Synthesis |
|---|---|
Use Scenario: Recovering audio from broadcast FM signals using a quadrature or ratio detector topology. IC Role / Device Role / Timing Role: 74HCT7046AN,112 acts as the core PLL demodulator - VCO tracks carrier frequency, DEMOUT extracts baseband audio. Use Value: 0.4% VCO linearity and ±20 mV DEMOUT offset ensure low-distortion audio recovery without post-filter trimming. | Use Scenario: Generating precise clock multiples (e.g., 4×, 8×) from a crystal reference in communication transceivers. IC Role / Device Role / Timing Role: 74HCT7046AN,112 serves as the PLL front-end - PC2 locks VCO to divided reference, VCOOUT feeds programmable divider chain. Use Value: PC2's zero-phase-error operation and 17 MHz center frequency support stable integer-N synthesis up to 136 MHz with minimal jitter. |
| Tone Decoding | Motor-Speed Control |
Use Scenario: Detecting DTMF or sub-audible tones in security systems and telephony interfaces. IC Role / Device Role / Timing Role: 74HCT7046AN,112 functions as a narrowband tone tracker - LD output triggers decode on lock, DEMOUT confirms amplitude. Use Value: Dual comparator selection allows PC1 for high-SNR tone detection or PC2 for fast acquisition of drifting tones. | Use Scenario: Regulating DC motor speed via closed-loop tachometer feedback in industrial actuators. IC Role / Device Role / Timing Role: 74HCT7046AN,112 implements analog VCO-based speed regulation - tachometer pulses drive SIGIN, DEMOUT controls PWM duty cycle. Use Value: Linear VCO transfer function (0.4% linearity) and 0.15%/K thermal stability ensure consistent RPM control across temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar phase-locked-loop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4046BE | CMOS-compatible but older 4000-series; lower max frequency (1.2 MHz typ.), no DEMOUT buffer, no PC2, higher VCO nonlinearity (±10%) | Limited to low-frequency tone decoding and basic frequency multiplication; unsuitable for FM demodulation above 100 kHz | Select only for legacy 3–15 V designs where cost outweighs performance; verify lock range with RC filter design |
| SN74LV4046A | Lower-voltage LV family (1.65–5.5 V); 12 MHz max center frequency; identical PC1/PC2 architecture and DEMOUT functionality | Better suited for mixed-voltage 3.3 V systems; reduced EMI due to slower edges; same PCB layout but lower supply headroom | Prefer for new 3.3 V designs requiring pin-compatible upgrade path; confirm VCO linearity (0.6%) meets system tolerance |
Compared with CD4046BE and SN74LV4046A, the 74HCT7046AN,112 offers superior 17 MHz operation, 0.4% VCO linearity, and matched DEMOUT voltage - making it optimal for high-fidelity FM demodulation and precision frequency synthesis where thermal stability and analog accuracy are critical.
Availability
74HCT7046AN,112 is available at Aetrix Electronics and suitable for FM demodulation, frequency synthesis, tone decoding, motor-speed control, and voltage-to-frequency conversion applications requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for 74HCT7046AN,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The 74HCT7046AN,112 belongs to the legacy 74HCT logic family - designed for TTL-compatible interfacing in mixed-signal timing and control systems requiring robust PLL functionality with low-power operation.
FAQ
What is the maximum operating frequency of the VCO in the 74HCT7046AN,112?
The 74HCT7046AN,112 achieves a typical VCO center frequency of 17 MHz at VCC = 4.5 V with R1 = 3 kΩ and C1 = 40 pF. Under optimized conditions (e.g., VCC = 6.0 V, R1 = 1 kΩ, C1 = 22 pF), operation up to 21 MHz is documented - though linearity degrades above 17 MHz. The device is not rated for continuous operation beyond its specified 17 MHz typical center frequency.
How does the DEMOUT pin on the 74HCT7046AN,112 differ from conventional PLL demodulator outputs?
The DEMOUT pin (10) on the 74HCT7046AN,112 provides a buffered replica of the VCOIN voltage - unlike conventional emitter-follower or open-collector demodulators that introduce ~0.7 V threshold drops. This matched voltage eliminates DC offset errors in low-pass filter design and improves lock detector accuracy, especially in precision voltage-to-frequency conversion applications.
Can the 74HCT7046AN,112 be used with a single-supply 3.3 V system?
The 74HCT7046AN,112 is specified for VCC = 4.5–5.5 V and is not guaranteed to operate reliably at 3.3 V. While the digital section may function down to 2.0 V, the VCO section requires ≥3.0 V and exhibits degraded linearity and reduced center frequency below 4.5 V. For 3.3 V systems, the SN74LV4046A is the recommended functional alternative.
What external components are mandatory for basic 74HCT7046AN,112 PLL operation?
Four external components are mandatory: (1) capacitor C1 (≥40 pF) between pins 6 and 7; (2) resistor R1 (3–300 kΩ) from pin 11 to GND; (3) lock detector capacitor CLD (value per Fig.32) between pin 15 and GND; and (4) a low-pass filter (e.g., R3/C2) between PC1OUT/PC2OUT and VCOIN. R2 is optional for frequency offset.
Does the 74HCT7046AN,112 support lock detection without external components?
No - the 74HCT7046AN,112 requires an external capacitor (CLD) connected between pin 15 (CLD) and pin 8 (GND) to enable functional lock detection. Without this capacitor, the LD output (pin 1) remains indeterminate. The CLD value determines lock detector hysteresis and response time, and must be selected based on loop dynamics per Figure 32 in the datasheet.
74HCT7046AN,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HCT
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Phase Lock Loop (PLL)
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:3
- Differential - Input:Output:
- No/No
- Frequency - Max:
- 21MHz
- Divider/Multiplier:
- No/No
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-DIP
74HCT7046AN,112 FAQ
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7.What is the process for return or replacement of 74HCT7046AN,112?
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1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HCT7046AN,112 part is unused and in its original packaging.
Return procedure for 74HCT7046AN,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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