onsemi 74LCX126MX
- Part No.:
- 74LCX126MX
- Manufacturer:
- onsemi
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LCX126MX.pdf
- Description:
- IC BUF NON-INVERT 3.6V 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,344
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Product details
Overview
74LCX126MX from ON Semiconductor is a low-voltage quad non-inverting buffer with 3-STATE outputs, 5V-tolerant I/O, and operation across 2.3V–3.6V VCC. It delivers 5.5ns max propagation delay at 3.3V, ±24mA drive capability at 3.0V, and supports live insertion/withdrawal in mixed-voltage systems interfacing 5V logic to 3V domains.
For engineers reviewing the 74LCX126MX datasheet, pinout, applications, or equivalent options, this device is selected for voltage-level translation, bus isolation, and hot-swap-capable I/O buffering where 5V tolerance, low static current (10µA), and DQFN packaging are critical design requirements.
Technical Context
The 74LCX126MX implements four independent non-inverting buffers, each controlled by a dedicated active-low output-enable (OE) input. All inputs and outputs tolerate up to 7V, enabling safe interfacing between legacy 5V subsystems and modern 3.3V/2.5V logic without external level shifters.
It features power-down high-impedance inputs and outputs, latch-up immunity per JEDEC 78, and ESD protection >2000V HBM. Fabricated in advanced CMOS, it achieves high-speed operation while maintaining sub-10µA quiescent supply current under static conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3V–3.6V - Enables direct use in 2.5V and 3.3V systems without regulators |
| Propagation Delay | 5.5ns max at VCC = 3.3V - Supports >100MHz bus timing in buffered data paths |
| I/O Voltage Tolerance | Up to 7V - Allows connection to 5V buses without damage or clamping diodes |
| Output Drive | ±24mA at VCC = 3.0V - Sufficient to drive multiple LVTTL or LCX loads |
| ICC (Quiescent) | 10µA max - Minimizes standby power in battery-backed or energy-sensitive systems |
| Package | DQFN-14 (2.5 × 3.0 mm) - Enables high-density PCB layouts with improved thermal performance vs SOIC/TSSOP |
| ESD Rating | >2000V HBM - Reduces handling sensitivity and improves manufacturing yield |
Pinout & Package
74LCX126MX is housed in a 14-terminal depopulated quad flat no-lead (DQFN) package per JEDEC MO-241, with exposed die attach pad (DAP) for thermal enhancement. Pin numbering follows standard top-view orientation with pin 1 marked by quadrant indicator.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Input (A1–A4) | Non-inverting data inputs; 5V tolerant, accept 0–7V swing |
| 2, 5, 11, 14 | Output Enable (OE1–OE4) | Active-low control; pull-up required during power-up to ensure Hi-Z state |
| 3, 6, 12, 9 | Output (Y1–Y4) | 3-STATE non-inverting outputs; Hi-Z when OE = LOW, full drive when OE = HIGH |
| 7 | GND | Ground reference for all logic and power domains |
| 14 | VCC | Primary supply rail (2.3–3.6V); powers internal logic and output drivers |
| DAP | Die Attach Pad | Thermally conductive exposed pad; must be soldered to PCB ground plane for optimal thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| 5V-tolerant I/O | Enables seamless interconnection between 3.3V microcontrollers and 5V peripherals without external translators |
| Live insertion support | Guarantees safe hot-plug operation via controlled Hi-Z on power ramp-no bus contention during insertion |
| Low ICC (10 µA) | Reduces system-level quiescent current in always-on interfaces such as sensor hubs or remote I/O modules |
| ±24 mA output drive | Drives ≥10 LVTTL loads or ≥4 LCX gates at 3.0V, eliminating need for buffer fanout stages |
| JEDEC MO-241 DQFN | 2.5 × 3.0 mm footprint saves >60% board area vs SOIC-14, with lower inductance and better signal integrity |
Applications
| Industrial PLC Backplane Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Isolating 5V sensor bus signals from 3.3V MCU I/O pins in programmable logic controller backplanes. IC Role / Device Role / Timing Role: Voltage-translating buffer with 3-STATE control for dynamic bus arbitration and hot-swap-safe module insertion. Use Value: Eliminates discrete level-shifter components while maintaining <5.5ns timing margin for 20 MHz synchronous bus cycles. |
Use Scenario: Interfacing legacy 5V LIN transceivers and dashboard switches to a 3.3V automotive microcontroller. IC Role / Device Role / Timing Role: Bidirectional I/O buffer enabling robust communication across mixed-supply domains in harsh electrical environments. Use Value: Withstands load-dump transients up to 7V and provides ±24mA drive for reliable switch debouncing and LED indicator control. |
| Medical Diagnostic Equipment Data Bus | Telecom Line Card Signal Conditioning |
|
Use Scenario: Buffering analog-to-digital converter interface lines in portable ultrasound units where low-power operation is mandatory. IC Role / Device Role / Timing Role: Low-quiescent-current (10µA) signal isolator preventing ground-loop coupling between analog front-end and digital processing sections. Use Value: Maintains signal fidelity with <8pF output capacitance and enables battery life extension via sub-µA standby current during idle periods. |
Use Scenario: Driving high-capacitance traces (>50pF) on dense telecom line card PCBs connecting FPGA I/O banks to external PHY devices. IC Role / Device Role / Timing Role: High-drive (±24mA) bus repeater ensuring signal integrity over long trace lengths with minimal skew (<1ns). Use Value: Meets AC timing specs (tPZH/tPHZ ≤7.8ns at 2.5V) for 50 Mbps parallel control bus operation without timing closure issues. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APWR | Lower VCC min (1.65V), but only 5.5V I/O tolerance - not 7V rated | Suitable for 1.8V–3.3V-only systems; lacks full 5V-bus survivability | Select when operating exclusively below 3.3V and cost is prioritized over 7V fault margin |
| 74ALVC126MTCX | Faster tPD (3.3ns @ 3.3V), but only 3.6V I/O tolerance and higher ICC (20µA) | Better for ultra-high-speed clock distribution, less suited for 5V legacy interface | Choose when propagation delay dominates design, and 5V tolerance is not required |
Compared with SN74LVC126APWR and 74ALVC126MTCX, the 74LCX126MX uniquely balances 7V I/O tolerance, 5.5ns speed, and 10µA ICC in a space-saving DQFN - making it optimal for mixed-voltage industrial and automotive interfaces where reliability under overvoltage stress is non-negotiable.
Availability
74LCX126MX is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, and medical diagnostic equipment requiring stable component supply with guaranteed long-term DQFN packaging continuity.
Supply support for 74LCX126MX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
ON Semiconductor is a global semiconductor manufacturer specializing in energy-efficient power management, analog, logic, and sensor solutions for automotive, industrial, and cloud infrastructure markets.
The 74LCX126MX belongs to the legacy LCX logic family, designed specifically for low-voltage, high-speed, 5V-tolerant interfacing in mixed-supply systems - bridging compatibility gaps between older and newer logic families without compromising timing or robustness.
FAQ
What is the maximum input voltage the 74LCX126MX can safely withstand?
The 74LCX126MX supports DC input voltages up to +7.0V, exceeding standard 5V TTL levels. This allows direct connection to 5V buses without risk of damage or latch-up, even during power sequencing mismatches. The 74LCX126MX maintains functional integrity across its full 0–7V input range while powered from 2.3–3.6V VCC.
Does the 74LCX126MX require external pull-up resistors on OE pins?
Yes - to guarantee high-impedance outputs during power-up or power-down, each OE pin must be tied to VCC via an external pull-up resistor. The minimum resistance value depends on the driver's sourcing capability; insufficient pull-up strength may cause unintended output activation. This requirement applies to every instance of the 74LCX126MX in system design.
Can the 74LCX126MX operate at 2.0V VCC?
No - the 74LCX126MX has a specified minimum VCC of 2.3V per its Recommended Operating Conditions table. Operation at 2.0V falls outside guaranteed specifications and may result in undefined logic states, increased propagation delay, or failure to meet AC timing parameters. The 74LCX126MX is validated only for 2.3–3.6V operation.
Is the DAP (Die Attach Pad) on the 74LCX126MX package electrically connected?
The DAP on the 74LCX126MX is internally connected to GND and must be soldered to a PCB ground plane for thermal and electrical stability. Leaving it unconnected degrades thermal performance and may increase junction temperature beyond safe limits during sustained ±24mA output operation. Proper grounding of the DAP is mandatory for reliable 74LCX126MX deployment.
How does the 74LCX126MX handle unused inputs?
Unused inputs on the 74LCX126MX must be held statically HIGH or LOW - floating inputs are prohibited per datasheet Note 4. Uncontrolled inputs increase ICC, induce oscillation, and raise EMI susceptibility. For unused channels, tie An to VCC or GND, and OEn to VCC (to force Hi-Z) or GND (to enable output). This rule applies uniformly across all 74LCX126MX units in production.
74LCX126MX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LCX
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 2V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
74LCX126MX FAQ
1.How can I place an order for 74LCX126MX through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LCX126MX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LCX126MX reliable?
The price and inventory of 74LCX126MX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LCX126MX is usually 5 days.
3.What payment methods are accepted for 74LCX126MX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LCX126MX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LCX126MX?
74LCX126MX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LCX126MX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LCX126MX?
For technical support, including 74LCX126MX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LCX126MX requirements.
6.How does Aetrix verify that 74LCX126MX is sourced from the original manufacturer or authorized distributors?
All 74LCX126MX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LCX126MX meets industry standards.
7.What is the process for return or replacement of 74LCX126MX?
All 74LCX126MX units undergo pre-shipment inspection (PSI). If there is an issue with 74LCX126MX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LCX126MX part is unused and in its original packaging.
Return procedure for 74LCX126MX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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