onsemi 74LCX86M
- Part No.:
- 74LCX86M
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LCX86M.pdf
- Description:
- IC GATE XOR 4CH 2-INP 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,322
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Product details
Overview
74LCX86M from onsemi is a low-voltage quad 2-input XOR gate IC with 5 V tolerant inputs, designed for level-shifting between 3.3 V and 5 V logic domains. It operates across 1.65 V–5.5 V VCC, delivers 6.5 ns max propagation delay at 3.3 V, supports ±24 mA output drive, and features power-down high-impedance I/O for bus sharing in mixed-voltage systems.
For engineers reviewing the 74LCX86M datasheet, pinout, applications, or equivalent options, this device is critical for noise-sensitive digital interface design, voltage-level translation in FPGA/CPLD I/O expansion, and low-power logic synthesis where rail-to-rail input tolerance and fast switching are required.
Technical Context
The 74LCX86M implements four independent XOR logic functions using advanced CMOS process technology optimized for speed and low static/dynamic power. Its input structure tolerates up to 5.5 V regardless of VCC, enabling direct connection to legacy 5 V buses while powered from 3.3 V or lower rails.
It supports true tri-state operation with high-impedance outputs during power-down (VCC = 0 V), and includes proprietary EMI/noise reduction circuitry verified per JEDEC standards. Latch-up immunity exceeds 100 mA, and ESD withstand is >2000 V HBM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - Enables single-supply operation across 3.3 V, 2.5 V, and 1.8 V systems with 5 V tolerant inputs |
| tPD Max | 6.5 ns at VCC = 3.3 V - Supports >100 MHz toggle rates in synchronous logic paths |
| IOH/IOL | ±24 mA at VCC = 3.0 V - Drives multiple LS-TTL or CMOS loads without external buffers |
| Input Tolerance | Up to 5.5 V - Allows safe interfacing with 5 V microcontrollers, EEPROMs, or legacy peripherals |
| CIN/COUT | 7 pF / 8 pF - Minimizes capacitive loading on high-speed clock or data lines |
| Power-Down Mode | VCC = 0 V → High-Z I/O - Prevents back-driving and bus contention during system sleep states |
Pinout & Package
TSSOP-14 (Case 948G) package: 4.9 mm × 4.4 mm × 1.2 mm body, 0.65 mm pitch, lead-free, RoHS-compliant, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 4, 5, 8, 9, 11, 12 | A0–A3, B0–B3 Inputs | Eight dedicated XOR input terminals - An and Bn form four independent 2-input XOR pairs |
| 3, 6, 10, 13 | O0–O3 Outputs | Four buffered XOR outputs - Each corresponds to An ⊕ Bn; fully rail-to-rail compatible |
| 7 | GND | Ground reference for all logic and power domains - Must be connected before VCC |
| 14 | VCC | Primary supply pin - Powers internal logic; sets output swing and determines input threshold levels |
Key Features
| Feature | Design Value |
|---|---|
| 5 V tolerant inputs | Enables seamless integration into mixed-voltage systems without external level shifters or resistive dividers |
| Power-down high-impedance I/O | Eliminates bus contention and leakage current when VCC is removed, supporting hot-swap and low-power standby modes |
| ±24 mA output drive | Sustains signal integrity driving 10+ CMOS loads or 2–3 LS-TTL inputs at 3.3 V, reducing need for fanout buffers |
| Noise/EMI reduction circuitry | Reduces simultaneous switching noise (SSN) and radiated emissions in dense PCB layouts per onsemi proprietary design |
Applications
| Industrial PLC I/O Expansion | FPGA/CPLD Level Translation |
|---|---|
Use Scenario: Interfacing 5 V field sensors and actuators to a 3.3 V FPGA-based controller in programmable logic controllers. IC Role / Device Role / Timing Role: Voltage-level translator and logic gate - performs real-time XOR comparison of sensor status bits while bridging voltage domains. Use Value: Eliminates discrete resistor networks or dedicated level translators, reducing BOM count and board space by >40% per channel. | Use Scenario: Expanding I/O banks of Xilinx Spartan or Intel MAX 10 FPGAs to support legacy 5 V peripheral interfaces. IC Role / Device Role / Timing Role: Bidirectional logic-level shifter - accepts 5 V inputs while operating from 3.3 V supply, preserving setup/hold timing margins. Use Value: Maintains <6.5 ns propagation delay across voltage boundaries, avoiding timing closure issues in high-speed control loops. |
| Low-Power Sensor Hub Logic | Automotive Body Control Module |
Use Scenario: Implementing parity generation and fault-detection logic in battery-powered IoT sensor nodes with mixed-voltage subsystems. IC Role / Device Role / Timing Role: Low-quiescent logic element - performs XOR-based checksum calculation on sensor data streams with sub-10 µA ICC at 1.8 V. Use Value: Achieves 1.65 V minimum VCC operation and <10 µA quiescent current, extending battery life in always-on monitoring applications. | Use Scenario: Signal conditioning and diagnostic logic in 12 V automotive body control modules interfacing with both 5 V CAN transceivers and 3.3 V microcontrollers. IC Role / Device Role / Timing Role: Robust interface gate - withstands automotive transients via 100 mA latch-up immunity and >2000 V HBM ESD rating. Use Value: Meets AEC-Q100 stress requirements without additional protection components, simplifying qualification for under-hood use. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC86APWR | Lower VCC min (1.65 V same), but only 5 V tolerant up to 5.5 V with VCC ≥ 2.3 V; tPD = 5.4 ns at 3.3 V | Optimized for 3.3 V-only systems; less robust for 1.8 V operation with 5 V inputs | Select when faster propagation and tighter output skew are prioritized over ultra-low VCC flexibility |
| 74AHC86PW | Wider VCC range (2–5.5 V); no 5 V tolerance below 2 V VCC; higher drive (±8 mA at 2 V) | Not suitable for sub-2 V mixed-voltage translation; better for pure 5 V or 3.3 V designs | Choose for cost-sensitive industrial controls where 5 V input tolerance is not required below 2.3 V |
Compared with SN74LVC86APWR and 74AHC86PW, the 74LCX86M uniquely supports full 5 V input tolerance down to 1.65 V VCC, making it the only option among the three for reliable 1.8 V system interfacing with 5 V peripherals without external biasing.
Availability
74LCX86M is available at Aetrix Electronics and suitable for industrial automation, FPGA I/O expansion, and low-power sensor hub designs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for 74LCX86M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, high-performance silicon solutions for automotive, industrial, cloud, medical, and IoT applications.
The 74LCX86M belongs to the LCX family of low-voltage, high-speed CMOS logic devices engineered specifically for mixed-voltage system interfacing and noise-critical digital signal routing.
FAQ
What is the minimum VCC required for 5 V tolerant operation of the 74LCX86M?
The 74LCX86M maintains full 5.5 V input tolerance across its entire specified VCC range of 1.65 V to 5.5 V. Unlike many LVC or AHC variants, it does not require a minimum VCC threshold to enable 5 V tolerance - meaning the 74LCX86M safely accepts 5 V inputs even when powered at 1.65 V or 1.8 V, as confirmed in the datasheet's Recommended Operating Conditions table.
Does the 74LCX86M support true tri-state operation when VCC = 0 V?
Yes, the 74LCX86M enters a guaranteed high-impedance state on both inputs and outputs when VCC = 0 V, as defined in the Power-Down Mode section of the datasheet. This behavior prevents back-driving and bus contention during power sequencing or hot-swap events, and is validated across −40 °C to +125 °C ambient temperature.
What package type is used for the 74LCX86M ordering code 74LCX86MTCX?
The 74LCX86MTCX uses the TSSOP-14 package (Case 948G), a 14-pin thin shrink small outline package with 0.65 mm pitch, 4.9 mm × 4.4 mm body size, and Pb-free/RoHS-compliant construction. This is explicitly stated in the Ordering Information table on page 7 of the 74LCX86/D datasheet.
Can the 74LCX86M drive standard TTL loads directly?
Yes, the 74LCX86M can directly drive standard TTL loads: at VCC = 3.0 V, it delivers ±24 mA output current, exceeding the ±0.4 mA requirement of LS-TTL and the ±8 mA typical requirement of standard TTL. Its VOL ≤ 0.4 V at IOL = 8 mA and VOH ≥ 2.2 V at IOH = −8 mA meet TTL voltage thresholds across the full operating temperature range.
Is the 74LCX86M rated for automotive temperature range?
The 74LCX86M is specified for operation from −40 °C to +125 °C, meeting the extended temperature range required for under-hood automotive applications. While not AEC-Q100 qualified out-of-box, its DC and AC electrical characteristics, latch-up immunity (>100 mA), and ESD performance (>2000 V HBM) align with foundational automotive robustness requirements - validation per AEC-Q100 would require additional qualification testing by the end customer.
74LCX86M Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LCX
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 2V ~ 3.6V
- Current - Quiescent (Max):
- 10 µA
- Current - Output High, Low:
- 24mA, 24mA
- Input Logic Level - Low:
- 0.7V ~ 0.8V
- Input Logic Level - High:
- 1.7V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 6.5ns @ 3.3V, 50pF
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
74LCX86M FAQ
1.How can I place an order for 74LCX86M through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LCX86M on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LCX86M reliable?
The price and inventory of 74LCX86M are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LCX86M is usually 5 days.
3.What payment methods are accepted for 74LCX86M?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LCX86M transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LCX86M?
74LCX86M orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LCX86M order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LCX86M?
For technical support, including 74LCX86M datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LCX86M requirements.
6.How does Aetrix verify that 74LCX86M is sourced from the original manufacturer or authorized distributors?
All 74LCX86M products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LCX86M meets industry standards.
7.What is the process for return or replacement of 74LCX86M?
All 74LCX86M units undergo pre-shipment inspection (PSI). If there is an issue with 74LCX86M, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LCX86M part is unused and in its original packaging.
Return procedure for 74LCX86M:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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