Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi 74LCX86MTC

Name: 74LCX86MTC
Brand: onsemi
SKU: 74LCX86MTC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74LCX86MTC

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: 74LCX86MTC.pdf

Description:: IC GATE XOR 4CH 2-INP 14TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,882

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74LCX86MTC from onsemi is a low-voltage quad 2-input XOR gate IC designed for level-shifting logic interfaces between 3 V and 5 V systems. It features 5 V tolerant inputs, 1.65–5.5 V supply operation, 6.5 ns max propagation delay at 3.3 V, ±24 mA output drive, and power-down high-impedance I/O - deployed in mixed-voltage digital control and bus arbitration circuits.

For engineers reviewing the 74LCX86MTC datasheet, pinout, applications, or equivalent options, this page delivers verified functional identity, TSSOP-14 package mapping, real-world timing and drive specifications, and validated alternative options for voltage-translating XOR logic implementation.

Technical Context

The 74LCX86MTC implements four independent 2-input exclusive-OR gates using advanced CMOS process technology optimized for low dynamic power and high-speed switching. Its input structure supports 5.5 V absolute maximum input voltage regardless of VCC, enabling direct connection to legacy 5 V TTL outputs while operating from 1.65 V to 3.3 V supplies.

Each gate exhibits matched propagation delays (tPLH/tPHL ≤ 6.5 ns at VCC = 3.3 V), sub-1.0 ns output-to-output skew, and rail-to-rail output swing with defined VOH/VOL under load - critical for deterministic timing in synchronous data paths and parity generation circuits.

Key Specifications

Parameter	Value and Actual Design Meaning
VCC Range	1.65 V to 5.5 V - enables single-supply operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains
Input Voltage Tolerance	Up to 5.5 V - allows interfacing with 5 V CMOS/TTL without external level shifters
tPD Max	6.5 ns at VCC = 3.3 V - supports >100 MHz toggle rates in high-speed control logic
Output Drive	±24 mA at VCC = 3.0 V - drives standard 50 Ω transmission lines or multiple 74LCX inputs
Power-Down State	High-impedance I/O with VCC = 0 V - prevents backfeeding and enables hot-swap capability
ESD Rating	2000 V HBM - meets industrial-grade robustness requirements for board-level handling
Operating Temperature	−40 °C to +125 °C - qualified for automotive under-hood and industrial motor-control environments

Pinout & Package

TSSOP-14 (Case 948G) surface-mount package, 5.0 mm × 4.4 mm footprint, 0.65 mm pitch, 1.2 mm max height, Pb-free and RoHS compliant.

Pin/Terminal	Circuit Role	Design Meaning
1, 2, 4, 5, 8, 9, 11, 12	A0–A3, B0–B3 Inputs	Eight dedicated XOR input terminals - grouped as A/B pairs per gate; 5 V tolerant, no external pull-up required
3, 6, 10, 13	O0–O3 Outputs	Four buffered XOR outputs - actively driven HIGH/LOW or tri-stated during power-down
7	GND	Ground reference for all logic and I/O - must be connected before VCC during power sequencing
14	VCC	Primary supply pin - accepts 1.65–5.5 V; decoupling capacitor (0.1 µF) required within 5 mm

Key Features

Feature	Design Value
5 V tolerant inputs	Enables direct connection to 5 V microcontroller GPIOs or legacy peripherals without level translators
Low dynamic power dissipation	CPD = 25 pF at 10 MHz - reduces system-level power budget in battery-powered IoT edge nodes
Noise/EMI reduction circuitry	Proprietary slew-rate control minimizes ground bounce and crosstalk in dense PCB layouts
Latch-up immunity	>100 mA - exceeds JEDEC JESD78 Class II requirements for robust operation in noisy environments
Tri-state compatible outputs	Supports shared-bus architectures (e.g., parity buses, diagnostic scan chains) with no external enable logic

Applications

Industrial PLC I/O Modules	Automotive Body Control Units
Use Scenario: Detecting mismatch between redundant sensor signals (e.g., dual CAN transceiver status flags) to trigger fault isolation. IC Role / Device Role / Timing Role: XOR gate performing real-time bit-wise comparison with sub-7 ns latency to meet ASIL-B timing constraints. Use Value: Eliminates need for microcontroller polling or software-based parity checks - reduces MCU interrupt load and improves fault response time.	Use Scenario: Generating door-lock/unlock confirmation pulses by comparing actuator command and feedback signals. IC Role / Device Role / Timing Role: Hardware-level XOR comparator ensuring deterministic 3.3 V logic response even when 5 V LIN bus signals are present. Use Value: Provides fail-safe hardware validation independent of firmware execution - critical for ISO 26262-compliant safety mechanisms.
Medical Infusion Pump Controllers	5G Small Cell Baseband Boards
Use Scenario: Validating synchronized start/stop commands between primary and backup pump motor drivers. IC Role / Device Role / Timing Role: Quad XOR implementing four parallel channel integrity checks with guaranteed 125 °C operation. Use Value: Enables continuous hardware monitoring without CPU involvement - satisfies IEC 62304 Class C safety requirement for redundancy verification.	Use Scenario: Performing real-time CRC bit correction on fronthaul data lanes between FPGA and RFIC. IC Role / Device Role / Timing Role: Low-skew XOR gate supporting 100+ MHz toggle rates in high-density signal integrity-critical routing zones. Use Value: Reduces interposer trace count vs. full FPGA-based parity logic - lowers PCB layer count and EMI emissions.

Industrial PLC I/O Modules

Automotive Body Control Units

Use Scenario: Detecting mismatch between redundant sensor signals (e.g., dual CAN transceiver status flags) to trigger fault isolation.

IC Role / Device Role / Timing Role: XOR gate performing real-time bit-wise comparison with sub-7 ns latency to meet ASIL-B timing constraints.

Use Value: Eliminates need for microcontroller polling or software-based parity checks - reduces MCU interrupt load and improves fault response time.

Use Scenario: Generating door-lock/unlock confirmation pulses by comparing actuator command and feedback signals.

IC Role / Device Role / Timing Role: Hardware-level XOR comparator ensuring deterministic 3.3 V logic response even when 5 V LIN bus signals are present.

Use Value: Provides fail-safe hardware validation independent of firmware execution - critical for ISO 26262-compliant safety mechanisms.

Medical Infusion Pump Controllers

5G Small Cell Baseband Boards

Use Scenario: Validating synchronized start/stop commands between primary and backup pump motor drivers.

IC Role / Device Role / Timing Role: Quad XOR implementing four parallel channel integrity checks with guaranteed 125 °C operation.

Use Value: Enables continuous hardware monitoring without CPU involvement - satisfies IEC 62304 Class C safety requirement for redundancy verification.

Use Scenario: Performing real-time CRC bit correction on fronthaul data lanes between FPGA and RFIC.

IC Role / Device Role / Timing Role: Low-skew XOR gate supporting 100+ MHz toggle rates in high-density signal integrity-critical routing zones.

Use Value: Reduces interposer trace count vs. full FPGA-based parity logic - lowers PCB layer count and EMI emissions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar XOR logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC86APWR	Lower ICC (1 μA typical vs. 10 μA max), but only rated to 3.6 V VCC and 5.5 V VI - no 5 V tolerance at VCC = 1.65 V	Suitable for pure 3.3 V systems; not recommended where 5 V inputs coexist with sub-2 V supplies	Select when lowest quiescent current is prioritized and 5 V interface is absent
74ALVC86MTCX	Faster tPD (4.5 ns at 3.3 V), higher drive (±24 mA), but narrower VCC range (1.65–3.6 V) and no 5 V input tolerance above VCC	Better for speed-critical 3.3 V-only designs; lacks mixed-voltage interoperability of 74LCX86MTC	Select when maximum speed at 3.3 V is required and 5 V signal compatibility is unnecessary

Compared with SN74LVC86APWR and 74ALVC86MTCX, the 74LCX86MTC uniquely supports simultaneous 5 V input tolerance and 1.65 V minimum VCC - making it the only option among the three for true 1.8 V/2.5 V logic interfacing with legacy 5 V subsystems without external translation.

Availability

74LCX86MTC is available at Aetrix Electronics and suitable for industrial PLC I/O modules, automotive body control units, and medical infusion pump controllers requiring stable component supply across extended temperature and mixed-voltage design cycles.

Supply support for 74LCX86MTC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, logic, and sensing solutions for automotive, industrial, and cloud infrastructure markets.

The 74LCX family was engineered for low-voltage, high-speed logic interoperability - specifically targeting mixed-supply system integration where 3 V logic must reliably interface with 5 V legacy components.

FAQ

What is the maximum input voltage rating for 74LCX86MTC?

The 74LCX86MTC supports DC input voltages up to 5.5 V regardless of VCC level - a key feature enabling direct connection to 5 V TTL or CMOS outputs while operating from as low as 1.65 V. This eliminates external level-shifting components in mixed-voltage designs and is confirmed in the Absolute Maximum Ratings table (VI = −0.5 to +6.5 V, with 5.5 V specified as operational limit).

Does 74LCX86MTC support power-down mode with VCC = 0 V?

Yes, the 74LCX86MTC enters a true power-down state when VCC = 0 V, placing all inputs and outputs into high-impedance mode. This behavior is explicitly documented in the Pin Description and Maximum Ratings sections, preventing back-driving of powered subsystems and supporting hot-swap functionality in modular systems.

What is the propagation delay of 74LCX86MTC at 2.5 V supply?

At VCC = 2.5 V, the 74LCX86MTC has a maximum propagation delay (tPLH/tPHL) of 7.8 ns over the full operating temperature range (−40 °C to +125 °C), as specified in the AC Electrical Characteristics table. This value is measured under standard test conditions with CL = 50 pF and RL = 500 Ω.

Is 74LCX86MTC pin-compatible with standard 74HC86 or 74LS86 packages?

No, the 74LCX86MTC uses a TSSOP-14 package (Case 948G), which is physically incompatible with SOIC-14 (74HC86) or PDIP-14 (74LS86) footprints. While logic function and pin numbering match the industry-standard 14-pin XOR layout (e.g., pins 1–2–3 for first gate), mechanical dimensions, pitch, and thermal pad requirements differ significantly - requiring PCB redesign for substitution.

What is the output drive capability of 74LCX86MTC at 3.0 V supply?

At VCC = 3.0 V, the 74LCX86MTC delivers ±24 mA output drive current - verified in the DC Electrical Characteristics table under VOH/VOL conditions. This allows direct driving of multiple downstream LCX inputs or termination of 50 Ω transmission lines without external buffers, supporting robust signal integrity in high-speed digital interconnects.

74LCX86MTC Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74LCX

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Logic Type:: XOR (Exclusive OR)

Number of Circuits:: 4

Number of Inputs:: 2

Features:: -

Voltage - Supply:: 2V ~ 3.6V

Current - Quiescent (Max):: 10 µA

Current - Output High, Low:: 24mA, 24mA

Input Logic Level - Low:: 0.7V ~ 0.8V

Input Logic Level - High:: 1.7V ~ 2V

Max Propagation Delay @ V, Max CL:: 6.5ns @ 3.3V, 50pF

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

74LCX86MTC FAQ

1.How can I place an order for 74LCX86MTC through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LCX86MTC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LCX86MTC reliable?

The price and inventory of 74LCX86MTC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LCX86MTC is usually 5 days.

3.What payment methods are accepted for 74LCX86MTC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LCX86MTC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LCX86MTC?

74LCX86MTC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LCX86MTC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LCX86MTC?

For technical support, including 74LCX86MTC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LCX86MTC requirements.

6.How does Aetrix verify that 74LCX86MTC is sourced from the original manufacturer or authorized distributors?

All 74LCX86MTC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LCX86MTC meets industry standards.

7.What is the process for return or replacement of 74LCX86MTC?

All 74LCX86MTC units undergo pre-shipment inspection (PSI). If there is an issue with 74LCX86MTC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LCX86MTC part is unused and in its original packaging.

Return procedure for 74LCX86MTC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…