Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

onsemi 74LCX86MX

Name: 74LCX86MX
Brand: onsemi
SKU: 74LCX86MX
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74LCX86MX

Manufacturer:: onsemi

Category:: Gates and Inverters

Package:: 14-SOIC (0.154", 3.90mm Width)

Datasheet:: 74LCX86MX.pdf

Description:: IC GATE XOR 4CH 2-INP 14SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,750

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74LCX86MX from onsemi is a low-voltage quad 2-input XOR gate IC with 5 V tolerant inputs, designed for level-shifting between 3.3 V and 5 V logic domains. It operates from 1.65 V to 5.5 V V_CC, delivers 6.5 ns max propagation delay at 3.3 V, supports ±24 mA output drive, and features power-down high-impedance I/O for bus-sharing applications in mixed-voltage embedded systems.

For engineers reviewing the 74LCX86MX datasheet, pinout, applications, or equivalent options, this device is selected for voltage-translating logic interfacing where low static current (10 µA max ICC), ESD robustness (>2000 V HBM), and latch-up immunity (>100 mA) are required in space-constrained SOIC-14 or TSSOP-14 layouts.

Technical Context

The 74LCX86MX implements four independent 2-input exclusive-OR functions using advanced CMOS process technology optimized for speed-power trade-off. Its input structure includes proprietary noise/EMI reduction circuitry and accepts voltages up to 5.5 V regardless of V_CC, enabling direct connection to legacy 5 V buses while powered from 3.3 V or lower supplies.

All four gates share identical AC/DC electrical characteristics across the full 1.65–5.5 V V_CC range and −40 °C to +125 °C operating temperature. Unused inputs must be tied to GND or V_CC; outputs enter high-impedance state during power-down (V_CC = 0 V), preventing back-driving.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	1.65 V to 5.5 V - enables interoperability across 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters
t_PD Max	6.5 ns at V_CC = 3.3 V - ensures timing-critical XOR operations (e.g., parity generation, error detection) meet sub-10 ns budgets
I_OH/I_OL	±24 mA at V_CC = 3.0 V - drives standard TTL loads or multiple CMOS inputs without external buffers
V_IH/V_IL	0.7×V_CC (min HI), 0.3×V_CC (max LO) at 4.5–5.5 V - guarantees reliable recognition of 5 V logic levels when V_CC ≥ 3.0 V
Power-down I/O State	High-impedance - allows safe insertion/removal in live-bus systems and eliminates contention during standby
ESD Rating	>2000 V HBM - meets industrial-grade handling requirements without additional protection circuitry

Pinout & Package

74LCX86MX is available in SOIC-14 (Case 751EF) and TSSOP-14 (Case 948G) packages - both 14-pin surface-mount outlines with 1.27 mm pitch (SOIC) or 0.65 mm pitch (TSSOP). Pin 1 is marked by a notch or dot; pin count and layout conform to JEDEC MS-012 and MO-153 standards.

Pin/Terminal	Circuit Role	Design Meaning
A0, A1, A2, A3	Input (XOR Gate A–D)	First operand per gate; 5 V tolerant - accepts 0–5.5 V signals regardless of V_CC
B0, B1, B2, B3	Input (XOR Gate A–D)	Second operand per gate; same 5 V tolerance and logic threshold behavior as A pins
O0, O1, O2, O3	Output (XOR Gate A–D)	Active-drive outputs with ±24 mA capability; tri-state during power-down (V_CC = 0 V)
V_CC	Supply Voltage	Single supply rail (1.65–5.5 V); powers all four gates and internal logic
GND	Ground Reference	Common return path for supply and I/O; decoupling capacitor required near pin

Key Features

Feature	Design Value
5 V Tolerant Inputs	Enables direct interface to 5 V microcontrollers, FPGAs, or legacy peripherals while operating from 3.3 V or lower supplies - eliminates discrete level translators
Low Propagation Delay	6.5 ns max at 3.3 V allows use in real-time parity checking, CRC computation, and synchronous data comparison circuits
Power-Down High-Z I/O	Prevents bus contention and back-powering during system sleep modes - critical for hot-swap and modular backplane designs
Robust ESD & Latch-up	2000 V HBM ESD rating and >100 mA latch-up immunity ensure reliability in noisy industrial environments without added protection components

Applications

Parity Generation	Data Path Comparison
Use Scenario: Generating even/odd parity bits for 4-bit data words in memory controllers or UART transceivers. IC Role / Device Role / Timing Role: XOR gate performing bitwise modulo-2 addition across parallel data lines. Use Value: Delivers deterministic 6.5 ns propagation delay at 3.3 V, ensuring parity validity within tight timing windows of synchronous memory interfaces.	Use Scenario: Comparing two 4-bit register outputs in microcontroller-based test equipment to detect mismatch conditions. IC Role / Device Role / Timing Role: Four independent XORs feeding OR logic to assert fault flag on any bit difference. Use Value: ±24 mA drive strength directly sinks OR-gate inputs, eliminating need for pull-up resistors or buffer stages.
Level-Shifted Bus Interface	Secure Key XOR Masking
Use Scenario: Interfacing a 3.3 V FPGA I/O bank to a 5 V sensor bus in automotive body control modules. IC Role / Device Role / Timing Role: Voltage-translating logic element maintaining signal integrity across mixed-supply domains. Use Value: 5 V tolerant inputs accept full 5 V swing from sensors; 3.3 V V_CC operation reduces system power and heat dissipation.	Use Scenario: Performing bitwise XOR between a stored encryption key and incoming plaintext in hardware security modules. IC Role / Device Role / Timing Role: Combinational logic block executing one round of simple substitution cipher masking. Use Value: Low 10 µA quiescent current minimizes leakage during idle periods, extending battery life in portable cryptographic devices.

Parity Generation

Data Path Comparison

Use Scenario: Generating even/odd parity bits for 4-bit data words in memory controllers or UART transceivers.

IC Role / Device Role / Timing Role: XOR gate performing bitwise modulo-2 addition across parallel data lines.

Use Value: Delivers deterministic 6.5 ns propagation delay at 3.3 V, ensuring parity validity within tight timing windows of synchronous memory interfaces.

Use Scenario: Comparing two 4-bit register outputs in microcontroller-based test equipment to detect mismatch conditions.

IC Role / Device Role / Timing Role: Four independent XORs feeding OR logic to assert fault flag on any bit difference.

Use Value: ±24 mA drive strength directly sinks OR-gate inputs, eliminating need for pull-up resistors or buffer stages.

Level-Shifted Bus Interface

Secure Key XOR Masking

Use Scenario: Interfacing a 3.3 V FPGA I/O bank to a 5 V sensor bus in automotive body control modules.

IC Role / Device Role / Timing Role: Voltage-translating logic element maintaining signal integrity across mixed-supply domains.

Use Value: 5 V tolerant inputs accept full 5 V swing from sensors; 3.3 V V_CC operation reduces system power and heat dissipation.

Use Scenario: Performing bitwise XOR between a stored encryption key and incoming plaintext in hardware security modules.

IC Role / Device Role / Timing Role: Combinational logic block executing one round of simple substitution cipher masking.

Use Value: Low 10 µA quiescent current minimizes leakage during idle periods, extending battery life in portable cryptographic devices.

Equivalent & Alternatives

The following parts are listed as comparable options for similar XOR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC86APWR	Same 14-pin TSSOP package; 1.65–3.6 V V_CC only; no 5 V input tolerance	Requires external level shifters for 5 V signal sources; suitable only in pure 3.3 V systems	Select when cost sensitivity outweighs mixed-voltage flexibility and board space permits added discretes
74AHC86PW,118	Higher V_CC range (2–5.5 V); 5 V tolerant inputs; 7.5 ns t_PD at 3.3 V	Slightly slower propagation but broader industrial temp support (−40 to +125 °C same as 74LCX86MX)	Choose when sourcing from NXP ecosystem or requiring AEC-Q200 qualification path

Compared with SN74LVC86APWR and 74AHC86PW,118, the 74LCX86MX uniquely combines 5 V input tolerance with sub-7 ns speed at 3.3 V and ultra-low ICC - making it optimal for compact, mixed-voltage embedded designs where timing, power, and interface simplicity are jointly constrained.

Availability

74LCX86MX is available at Aetrix Electronics and suitable for parity generation, level-shifted bus interfacing, data path comparison, and secure key masking applications requiring stable component supply across automotive, industrial control, and communications equipment lifecycles.

Supply support for 74LCX86MX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.

The 74LCX family was engineered for low-voltage, high-speed logic interfacing in mixed-supply systems - specifically targeting voltage translation, bus isolation, and timing-critical combinational logic in space- and power-constrained embedded platforms.

FAQ

What is the maximum supply voltage for the 74LCX86MX?

The 74LCX86MX supports a DC supply voltage (V_CC) from −0.5 V to +6.5 V, with recommended operation from 1.65 V to 5.5 V. Absolute maximum rating ensures robustness against transient overvoltage events, but sustained operation above 5.5 V risks permanent damage and violates JEDEC compliance limits.

Does the 74LCX86MX require external pull-up or pull-down resistors on unused inputs?

Yes - unused inputs on the 74LCX86MX must be tied to either GND or V_CC to prevent floating states that cause excessive current draw, logic instability, or increased EMI. The datasheet explicitly prohibits leaving inputs unconnected, as CMOS inputs exhibit high impedance and susceptibility to noise-induced switching.

Can the 74LCX86MX drive standard TTL loads directly?

Yes - the 74LCX86MX delivers ±24 mA output drive at V_CC = 3.0 V, exceeding the ±0.4 mA sink/source requirement of standard TTL (74LS) inputs. This allows direct fan-out to up to 60 LS-TTL loads or multiple modern CMOS inputs without buffering, provided V_CC ≥ 3.0 V and load capacitance remains ≤50 pF.

Is the 74LCX86MX RoHS compliant and lead-free?

Yes - the 74LCX86MX is Pb-Free, Halogen Free/BFR Free, and fully RoHS compliant per EU Directive 2011/65/EU. The "G" suffix in marking (e.g., LCX86G) and packaging documentation confirms lead-free finish; MSL Level 1 rating indicates unlimited floor life under dry storage conditions.

What is the thermal resistance (θ_JA) of the 74LCX86MX in SOIC-14 package?

The 74LCX86MX in SOIC-14 package (Case 751EF) has a junction-to-ambient thermal resistance (θ_JA) of 116 °C/W under standard JEDEC test conditions (2-ounce copper, 76 mm × 114 mm board, no airflow). This value assumes proper PCB thermal design - including adequate copper pour and vias - to maintain junction temperature below +150 °C under worst-case power dissipation.

74LCX86MX Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74LCX

Package/Case:: 14-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: XOR (Exclusive OR)

Number of Circuits:: 4

Number of Inputs:: 2

Features:: -

Voltage - Supply:: 2V ~ 3.6V

Current - Quiescent (Max):: 10 µA

Current - Output High, Low:: 24mA, 24mA

Input Logic Level - Low:: 0.7V ~ 0.8V

Input Logic Level - High:: 1.7V ~ 2V

Max Propagation Delay @ V, Max CL:: 6.5ns @ 3.3V, 50pF

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-SOIC

74LCX86MX FAQ

1.How can I place an order for 74LCX86MX through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LCX86MX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LCX86MX reliable?

The price and inventory of 74LCX86MX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LCX86MX is usually 5 days.

3.What payment methods are accepted for 74LCX86MX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LCX86MX transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LCX86MX?

74LCX86MX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LCX86MX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LCX86MX?

For technical support, including 74LCX86MX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LCX86MX requirements.

6.How does Aetrix verify that 74LCX86MX is sourced from the original manufacturer or authorized distributors?

All 74LCX86MX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LCX86MX meets industry standards.

7.What is the process for return or replacement of 74LCX86MX?

All 74LCX86MX units undergo pre-shipment inspection (PSI). If there is an issue with 74LCX86MX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LCX86MX part is unused and in its original packaging.

Return procedure for 74LCX86MX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…