Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters

Nexperia USA Inc. 74LV02PW,112

Name: 74LV02PW,112
Brand: Nexperia USA Inc.
SKU: 74LV02PW,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74LV02PW,112

Manufacturer:: Nexperia USA Inc.

Category:: Gates and Inverters

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: 74LV02PW,112.pdf

Description:: IC GATE NOR 4CH 2-INP 14TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,158

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74LV02PW,112 from Nexperia is a low-voltage Si-gate CMOS quad 2-input NOR gate operating from 1.0 V to 5.5 V supply, delivering 14-pin TSSOP package with −40 °C to +125 °C temperature rating, 6.0 ns typical propagation delay at 3.3 V/15 pF, and TTL-level input compatibility at 2.7–3.6 V - used in digital logic interfacing, bus arbitration, and enable/disable control in industrial microcontroller peripherals.

For engineers reviewing the 74LV02PW,112 datasheet, 74LV02PW,112 pinout, 74LV02PW,112 application, or 74LV02PW,112 equivalent, this page delivers verified functional identity, validated pin mapping, confirmed static/dynamic electrical specs, real-world use cases, and technically differentiated alternatives - all grounded in Nexperia's Rev. 04 product data sheet.

Technical Context

The 74LV02PW implements four independent 2-input NOR gates in a single monolithic CMOS die, with input thresholds compliant to TTL levels when VCC is 2.7–3.6 V and full rail-to-rail output swing across its 1.0–5.5 V operating range. Each gate follows the standard NOR truth table (L/L → H, L/H → L, H/L → L, H/H → L).

It features robust ESD protection (HBM >2000 V, MM >200 V), ground bounce <0.8 V and VOH undershoot >2 V at 3.3 V/25 °C, and operates reliably over extended industrial temperature extremes (−40 °C to +125 °C) without derating below 70 °C.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Function	Quad 2-input NOR - enables compact implementation of four independent OR-invert logic paths
Supply Voltage Range	1.0 V to 5.5 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V systems
Propagation Delay	6.0 ns typical at VCC = 3.3 V, CL = 15 pF - ensures timing-critical combinational logic meets sub-10 ns budget
Input Compatibility	TTL-level inputs accepted at VCC = 2.7–3.6 V - eliminates need for level-shifting when interfacing legacy 5 V logic
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and high-reliability embedded control
Power Dissipation	500 mW max (TSSOP14) - enables stable operation in thermally constrained PCB layouts without forced cooling
ESD Rating	HBM >2000 V, MM >200 V - provides inherent handling robustness during manual assembly and board-level integration

Pinout & Package

TSSOP14 plastic thin shrink small outline package (SOT402-1); 14-lead, 4.4 mm body width, 0.65 mm pitch; lead-free and RoHS-compliant.

Pin/Terminal	Circuit Role	Design Meaning
1	1Y	Output of Gate 1 - drives downstream logic or bus line with rail-to-rail CMOS swing
2	1A	Input A of Gate 1 - accepts TTL or CMOS logic levels per VCC condition
3	1B	Input B of Gate 1 - dual-input NOR requires both low for high output
4	2Y	Output of Gate 2 - electrically isolated from Gate 1; shares no internal nodes
5	2A	Input A of Gate 2 - independently configurable; no crosstalk with other gates
6	2B	Input B of Gate 2 - supports asynchronous logic combining or enable gating
7	GND	Digital ground reference - must be low-impedance connection to minimize noise coupling
8	3A	Input A of Gate 3 - usable for inverted signal generation or active-low decoding
9	3B	Input B of Gate 3 - paired with 3A to implement 2-input NOR function
10	3Y	Output of Gate 3 - capable of driving ≥6 mA load at 3.0 V (VOL ≤ 0.4 V)
11	4A	Input A of Gate 4 - supports redundant logic or multi-channel control
12	4B	Input B of Gate 4 - enables four independent decision points in one footprint
13	4Y	Output of Gate 4 - matches VOH ≥2.82 V / VOL ≤0.25 V at 3.0 V/6 mA
14	VCC	Positive supply rail - decoupling capacitor (100 nF) required within 5 mm of pin

Key Features

Feature	Design Value
Wide supply voltage range	1.0 V to 5.5 V - allows single part number deployment across mixed-voltage system domains
Low ground bounce	<0.8 V at 3.3 V/25 °C - reduces simultaneous switching noise in dense logic arrays
High-speed propagation	6.0 ns typical at 3.3 V/15 pF - meets timing closure for 100+ MHz clock domain control logic
TTL input compatibility	Valid at VCC = 2.7–3.6 V - simplifies migration from 74HCT02 in legacy designs
Extended temperature grade	−40 °C to +125 °C - certified for engine control units, motor drives, and outdoor infrastructure

Applications

Industrial PLC I/O Expansion

Automotive Body Control Module

Use Scenario: Adding discrete logic for status flag combination and interrupt masking in modular I/O racks.

IC Role / Device Role / Timing Role: NOR gate performs active-low OR logic to consolidate multiple fault signals into a single interrupt line.

Use Value: Eliminates need for FPGA or MCU GPIO expansion by enabling hardware-level signal aggregation with <6 ns latency.

Use Scenario: Implementing door lock enable/disable logic responsive to key fob, ignition state, and sensor inputs.

IC Role / Device Role / Timing Role: Quad NOR executes combinatorial safety interlocks - e.g., "lock if door closed AND ignition off AND no key present".

Use Value: Provides deterministic, fail-safe response without software execution delay or firmware update dependency.

Medical Infusion Pump Control

Test Equipment Signal Conditioning

Use Scenario: Generating pump motor enable signals conditioned on occlusion detection, battery voltage, and user command.

IC Role / Device Role / Timing Role: NOR gate acts as hardware-based safety gate - output goes low only when all conditions are satisfied.

Use Value: Meets IEC 62304 Class C requirement for hardware-enforced shutdown path independent of main processor.

Use Scenario: Converting TTL-compatible trigger outputs from oscilloscopes or logic analyzers to CMOS-level inputs for DUT synchronization.

IC Role / Device Role / Timing Role: Level-shifting NOR stage adapts signal polarity and voltage domain while preserving edge integrity.

Use Value: Enables reliable cross-platform triggering without external resistive dividers or dedicated level translators.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad 2-input NOR gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74LVC02PW,118	Higher drive strength (±24 mA vs ±12 mA at 3.3 V); identical pinout and logic function	Better suited for heavier capacitive loads (>30 pF) or longer trace routing	Select when output loading exceeds 15 pF or fan-out >10 standard loads
SN74LV02APWR	TI variant with tighter VOH/VOL specs at 2.5 V; same 14-pin TSSOP package	Preferred for mixed 2.5 V/3.3 V systems requiring guaranteed 2.5 V logic-high margin	Choose when interoperability with TI-based subsystems or 2.5 V ASIC interfaces is required

Compared with 74LV02PW,112, the 74LVC02PW,118 offers higher output current for driving larger loads, while SN74LV02APWR provides enhanced 2.5 V compatibility - both retain identical pinout and function but differ in drive capability and voltage-margin assurance.

Availability

74LV02PW,112 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, medical infusion pump safety logic, and test equipment signal conditioning requiring stable component supply across extended temperature ranges and mixed-voltage environments.

Supply support for 74LV02PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert headquartered in Nijmegen, Netherlands, specializing in high-volume, high-reliability logic, analog, and discrete components for industrial, automotive, and consumer markets.

The 74LV logic family targets low-voltage, mixed-supply digital systems - designed specifically to replace legacy 74HC/HCT devices while maintaining pin and function compatibility and extending operational range down to 1.0 V.

FAQ

What is the maximum recommended supply voltage for continuous operation?

The absolute maximum supply voltage is +7.0 V per limiting values table, but the recommended operating maximum is +5.5 V. Operation above 5.5 V risks permanent damage even for brief transients, and the device is not characterized or guaranteed beyond that limit - sustained use at 5.5 V is fully supported across the full temperature range.

Can 74LV02PW,112 interface directly with 5 V TTL outputs?

No - it does not accept 5 V inputs when powered at ≤3.6 V. However, when VCC is set to 2.7–3.6 V, it accepts TTL input levels (0.8 V VIH min, 2.0 V VIL max), making it compatible with 3.3 V TTL outputs. For true 5 V TTL input tolerance, a level shifter or 74HCT02 is required.

Is thermal pad connection required for the TSSOP14 package?

No - unlike QFN packages, the TSSOP14 (SOT402-1) has no exposed thermal pad. The package relies on lead-frame conduction and PCB copper area for thermal dissipation. Standard reflow profile for lead-free solder applies, with peak temperature ≤260 °C.

Does the device support partial power-down or Ioff protection?

No - the 74LV02PW,112 lacks Ioff (power-off protection) circuitry. When VCC = 0 V, inputs and outputs may draw excessive current if driven externally. For hot-swap or partial-power-down applications, an Ioff-enabled alternative like 74LVC02 must be selected.

74LV02PW,112 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74LV

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: NOR Gate

Number of Circuits:: 4

Number of Inputs:: 2

Features:: -

Voltage - Supply:: 1V ~ 5.5V

Current - Quiescent (Max):: 40 µA

Current - Output High, Low:: 12mA, 12mA

Input Logic Level - Low:: 0.3V ~ 0.8V

Input Logic Level - High:: 0.9V ~ 2V

Max Propagation Delay @ V, Max CL:: 6ns @ 5V, 50pF

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

74LV02PW,112 FAQ

1.How can I place an order for 74LV02PW,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LV02PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LV02PW,112 reliable?

The price and inventory of 74LV02PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV02PW,112 is usually 5 days.

3.What payment methods are accepted for 74LV02PW,112?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV02PW,112 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LV02PW,112?

74LV02PW,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LV02PW,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LV02PW,112?

For technical support, including 74LV02PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV02PW,112 requirements.

6.How does Aetrix verify that 74LV02PW,112 is sourced from the original manufacturer or authorized distributors?

All 74LV02PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV02PW,112 meets industry standards.

7.What is the process for return or replacement of 74LV02PW,112?

All 74LV02PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV02PW,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LV02PW,112 part is unused and in its original packaging.

Return procedure for 74LV02PW,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

2026-08-11 LDO Regulator: Dropout Voltage, Noise, PSRR and Power Dissipation

LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…

2026-08-06 Conditional Access Module: CAM, CI/CI+ and DVB Security

Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…

2026-08-03 Electronic Component Obsolescence: EOL Risks, Replacement Options and Last-Time Buy Strategy

Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.

2026-07-29 18650 Battery: Voltage, Capacity, Charging and Pack Design

18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…

2026-07-27 Hall Effect Sensor: Working Principle, Types, Circuits and Applications

Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…

2026-07-20 Product Change Notification (PCN) in Electronic Components: Meaning and Supply Chain Response

Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…

2026-07-19 Blend Door Actuator: Symptoms, Location, Reset and Replacement Guide

A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…

2026-07-17 Raspberry Pi Alternatives: Chip-Level Comparison, Compatibility and Replacement Guide

Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…