Nexperia USA Inc. 74LV04BQ,115

Overview

74LV04BQ from Nexperia is a hex CMOS inverter IC operating across 1.0 V to 5.5 V supply, delivering six independent logic inversion functions with TTL-compatible inputs at VCC = 2.7–3.6 V, typical propagation delay of 6 ns at VCC = 3.3 V and CL = 15 pF, and output drive capability of ±12 mA, used for signal conditioning and level translation in low-voltage digital control subsystems.

For engineers reviewing the 74LV04BQ datasheet, 74LV04BQ pinout, 74LV04BQ application, or 74LV04BQ equivalent, this page provides verified functional identity, DHVQFN14 package mapping, validated static/dynamic electrical parameters, confirmed thermal rating (−40 °C to +125 °C), and real-world interface use cases - all extracted from Nexperia's Rev. 6 product data sheet dated 17 April 2024.

Technical Context

The 74LV04BQ implements six independent unbuffered inverters in a single monolithic CMOS structure, each with input clamp diodes enabling safe interfacing to voltages exceeding VCC when current-limiting resistors are used. Its logic function strictly follows the truth table: L → H, H → L, with no hysteresis or Schmitt-trigger behavior.

It supports mixed-voltage system interfacing via wide VCC range (1.0–5.5 V) and dual-level input compatibility: guaranteed TTL recognition at VCC = 2.7–3.6 V and full CMOS thresholds otherwise. Output stages are designed for rail-to-rail swing with VOH > 2.0 V (at VCC = 3.3 V, IO = −6 mA) and VOL < 0.40 V (at VCC = 3.0 V, IO = 6 mA).

Key Specifications

Pinout & Package

DHVQFN14 (SOT762-1) package: 2.5 × 3.0 × 0.85 mm body, 14-terminal quad flat no-lead construction with exposed thermal pad (non-electrical, optional VCC or floating connection). Pin 1 index area marked on top surface.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex inverter applications.

Compared with SN74LVC04APWR and 74AUP04GW,118, the 74LV04BQ uniquely balances 1.0 V operability, built-in overvoltage input clamping, and −40 °C to +125 °C qualification - making it the only option among the three suitable for automotive body electronics with mixed-voltage sensor interfacing.

Availability

74LV04BQ is available at Aetrix Electronics and suitable for industrial PLC I/O conditioning, USB-C power delivery logic interface, and automotive body control module designs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LV04BQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile applications.

The 74LV04BQ belongs to Nexperia's LV (Low-Voltage) logic family, engineered specifically for robust interoperability across 1.0–5.5 V supply domains while maintaining industry-standard pinouts and timing behavior.

FAQ

Is the exposed thermal pad on the DHVQFN14 package electrically connected?

No. The exposed pad on the 74LV04BQ's SOT762-1 package is not electrically connected to any internal node. Nexperia explicitly states it has no electrical or mechanical requirement to solder the pad; if soldered, it must remain floating or be tied to VCC - never to GND or another potential.

Can 74LV04BQ safely interface with 5 V TTL outputs when powered at 3.3 V?

Yes. At VCC = 2.7–3.6 V, the 74LV04BQ accepts standard TTL input levels (VIH ≥ 2.0 V, VIL ≤ 0.8 V), and its input clamp diodes protect against momentary overshoot. With a 1 kΩ series resistor, a 5 V TTL output drives the input within absolute maximum ratings (IIK ≤ ±20 mA).

What is the maximum capacitive load the 74LV04BQ can drive while maintaining 6 ns propagation delay?

The 6 ns typical tpd is specified at CL = 15 pF. Driving larger loads increases delay nonlinearly: at CL = 30 pF, tpd rises to ~9 ns (per Nexperia's dynamic characteristics curves). For timing-critical paths, keep total load (including trace and input capacitance) ≤15 pF or recalculate using CPD = 21 pF and the dynamic power formula.

Does the 74LV04BQ support partial power-down operation with unused gates?

No. The 74LV04BQ has no individual gate disable or power-gating feature. All six inverters share VCC and GND. To minimize leakage, unused inputs must be tied HIGH or LOW (not left floating), and unused outputs should be left open - no internal isolation exists between gates.