Nexperia USA Inc. 74LV123D,118

Overview

74LV123D,118 from Nexperia is a dual retriggerable monostable multivibrator with independent reset inputs, designed for precise pulse generation and timing extension in low-voltage digital systems. It operates from 1.0 V to 5.5 V, supports both negative- and positive-edge triggering on A/B inputs, delivers programmable output pulse widths via external R_EXT/C_EXT, and features Schmitt-trigger inputs for noise immunity. It is used in industrial control logic, power sequencing, and debounce circuits where adjustable, extendable timing pulses are required.

For engineers reviewing the 74LV123D,118 datasheet, 74LV123D,118 pinout, 74LV123D,118 application, or 74LV123D,118 equivalent, key selection criteria include its dual-channel retriggerability, 16-pin SO16 package compatibility, -40 °C to +125 °C temperature rating, TTL-input compatibility at 2.7–3.6 V, and direct asynchronous reset functionality per channel.

Technical Context

The 74LV123D implements two independent monostable multivibrators, each with separate edge-triggered inputs (A: negative-edge, B: positive-edge), active-low reset (RD), and complementary outputs (Q and Q̅). Pulse width is externally set by R_EXT and C_EXT connected to dedicated pins (e.g., 1REXT/CEXT and 1CEXT), enabling nanosecond-to-microsecond timing ranges.

Retriggering extends the output pulse indefinitely-each new valid trigger edge restarts the timing cycle-while a LOW-going edge on RD terminates the pulse immediately. Schmitt-trigger action on A/B inputs ensures robust operation with slow-rising signals, and internal clamp diodes allow safe interfacing to voltages exceeding V_CC when current-limiting resistors are used.

Key Specifications

Pinout & Package

74LV123D,118 is housed in a plastic small outline package (SO16) per SOT109-1, with 16 leads, 3.9 mm body width, and standard 1.27 mm lead pitch. Pin 1 is marked by a notch or index area; the package is RoHS-compliant and rated for reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Compared with 74LV123PW,118, the 74LV123D,118 offers lower thermal resistance and easier hand-soldering, while SN74LV123AD trades minor timing variance for supply-chain continuity in TI-centric ecosystems.

Availability

74LV123D,118 is available at Aetrix Electronics and suitable for industrial motor control, automotive power sequencing, medical instrument debounce, and test equipment signal gating requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LV123D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LV123 belongs to Nexperia's LV (Low-Voltage) logic family, engineered for robust operation across 1.0–5.5 V supplies with optimized speed-power trade-offs for timing-critical embedded systems.

FAQ

What is the minimum external capacitor value needed for stable operation?

The datasheet specifies no lower limit for C_EXT, but for accurate pulse width calculation, C_EXT > 10 nF is recommended. At smaller values (e.g., 100 pF), inherent pin capacitance (~7 pF) dominates, causing deviation from the K·R·C formula. Use C_EXT ≥ 1 nF with tight tolerance (±5%) and low-ESR ceramic types for repeatable timing below 100 ns.

Can both trigger inputs (A and B) be used simultaneously on one channel?

Yes-inputs 1A and 1B operate independently on channel 1: a falling edge on 1A or rising edge on 1B will trigger or retrigger the monostable. They are not OR'd internally; either can extend the pulse. However, simultaneous edges do not alter timing behavior-the latest valid edge determines the restart point.

How does the reset input interact with an ongoing retriggered pulse?

A LOW-going edge on 1RD or 2RD forces the corresponding Q output LOW and Q̅ HIGH immediately, terminating the pulse regardless of retrigger activity. The internal state resets completely-no residual timing remains-and the channel waits for the next valid A/B edge to begin a new cycle.

Is the 74LV123D,118 suitable for use with 1.2 V FPGA I/O banks?

Yes-it is fully specified down to V_CC = 1.2 V, with guaranteed VIH/VIL thresholds and 120 ns max propagation delay. At 1.2 V, output drive is reduced (~1 mA), so ensure fanout ≤2 LVCMOS12 loads and use short traces (<2 cm) to maintain signal integrity and timing accuracy.