Nexperia USA Inc. 74LV123PW,118
- Part No.:
- 74LV123PW,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Multivibrators
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74LV123PW,118.pdf
- Description:
- IC MULTIVIBRATOR 14NS 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LV123PW,118 from Nexperia is a dual retriggerable monostable multivibrator with independent reset inputs, operating from 1.0 V to 5.5 V supply. It generates programmable output pulses via external REXT/CEXT networks (e.g., 450 µs typical at VCC = 3.3 V, REXT = 10 kΩ, CEXT = 100 nF), supports edge-triggered retriggering on both rising and falling edges at A/B inputs, and features Schmitt-trigger inputs for noise immunity in industrial timing control circuits.
For engineers reviewing the 74LV123PW,118 datasheet, 74LV123PW,118 pinout, 74LV123PW,118 application, or 74LV123PW,118 equivalent, key selection criteria include its dual-channel retriggerable pulse extension capability, direct asynchronous reset termination, wide-voltage CMOS compatibility (1.0–5.5 V), -40 °C to +125 °C operation, and TSSOP16 package suitability for space-constrained PCB layouts.
Technical Context
The 74LV123PW,118 implements two independent monostable circuits, each with separate negative-edge (nA) and positive-edge (nB) trigger inputs, active-low direct reset (nRD), and complementary outputs (nQ/nQ). Pulse width is externally set by REXT and CEXT connected to dedicated pins (nREXT/CEXT and nCEXT), enabling precise timing from nanoseconds to milliseconds.
Retriggering extends the output pulse indefinitely while maintaining 100 % duty factor capability; reset input (nRD) terminates the pulse asynchronously regardless of timing state. Schmitt-trigger action on nA/nB inputs ensures robust operation with slow-rising signals, while internal clamp diodes allow interface to voltages exceeding VCC using current-limiting resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.0 V to 5.5 V - Enables interoperability across 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| Operating Temperature | -40 °C to +125 °C - Qualified for under-hood automotive, industrial motor control, and high-ambient embedded systems. |
| Pulse Width Range | 70 ns to >1 ms - Programmable via external REXT (2–1000 kΩ) and CEXT (no upper limit); 450 µs typical at VCC = 3.3 V, REXT = 10 kΩ, CEXT = 100 nF. |
| Propagation Delay | 14 ns to 92 ns - tPD from nRD/nA/nB to nQ/nQ varies with VCC (e.g., 25 ns typ at VCC = 3.3 V, -40 °C to +85 °C). |
| Input Thresholds | VIH = 0.7VCC (min), VIL = 0.3VCC (max) - TTL-compatible thresholds at VCC ≥ 2.7 V; Schmitt-trigger hysteresis on nA/nB inputs improves noise margin. |
| Output Drive | ±12 mA at VCC = 4.5 V - Sufficient to directly drive LEDs, small relays, or logic fan-out without buffers. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - Meets JEDEC JS-001 Class 2 and JS-002 Class C3 for robust handling in manufacturing and field environments. |
Pinout & Package
TSSOP16 plastic thin shrink small outline package (SOT403-1), 16-pin, 4.4 mm body width, 0.65 mm pitch, lead-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Negative-edge triggered input | Triggers monostable on HIGH-to-LOW transition; enables synchronization with falling-edge clock or control signals. |
| 1B, 2B | Positive-edge triggered input | Triggers monostable on LOW-to-HIGH transition; supports rising-edge event detection (e.g., button press, sensor activation). |
| 1RD, 2RD | Direct reset input | Asynchronously forces nQ = LOW / nQ = HIGH on LOW-going edge; terminates ongoing pulse regardless of retrigger state. |
| 1Q, 2Q | Active HIGH output | Provides non-inverted output pulse; drives logic loads, microcontroller interrupts, or enable lines directly. |
| 1Q, 2Q | Active LOW output | Complementary inverted output; simplifies interfacing with active-low enable inputs or reset circuits. |
| 1REXT/CEXT, 2REXT/CEXT | Timing resistor/capacitor node | Connects external REXT and CEXT to define base pulse width; internal RC network sets timing constant K (0.45–0.48). |
| 1CEXT, 2CEXT | External capacitor connection | Second capacitor terminal for timing network; grounding these pins minimizes noise coupling into timing path. |
| VCC (Pin 16) | Supply voltage | Single 1.0–5.5 V rail powers both channels; decoupling capacitor required near pin for stable operation. |
| GND (Pin 8) | Ground reference | Common return for all internal circuitry and external timing components; must be low-impedance connection. |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable pulse extension | Enables indefinite pulse stretching via repeated nA/nB triggers - ideal for watchdog timeout extension or variable-duration enable signals. |
| Independent channel reset | Each monostable has dedicated nRD input allowing selective termination without affecting the other channel - critical for multi-function timing in PLC I/O modules. |
| Wide-voltage CMOS operation | Functions reliably from 1.0 V (ultra-low-power battery systems) to 5.5 V (legacy 5 V microcontrollers) - eliminates need for multiple voltage families. |
| Schmitt-trigger inputs | nA/nB inputs tolerate slow rise/fall times (>50 ns/V at VCC = 5.5 V) - reduces sensitivity to EMI and eliminates need for external signal conditioning. |
| Clamp diode protection | Allows safe interfacing to voltages above VCC using series resistors - simplifies mixed-voltage board design (e.g., 3.3 V IC driving 5 V sensor signals). |
Applications
| Industrial Motor Control | Automotive Body Electronics |
|---|---|
|
Use Scenario: Generating timed enable pulses for stepper motor drivers during position homing sequences. IC Role / Device Role / Timing Role: Dual-channel monostable provides synchronized start/stop timing for two-axis motion control, with independent reset for emergency stop override. Use Value: Eliminates microcontroller GPIO overhead for pulse generation; retriggering allows dynamic adjustment of dwell time based on encoder feedback. |
Use Scenario: Debouncing and timing window generation for door lock/unlock switch inputs in central body controllers. IC Role / Device Role / Timing Role: Each channel processes one switch pair (lock/unlock), generating clean, noise-immune pulses with programmable hold duration. Use Value: Schmitt-trigger inputs reject contact bounce; independent reset allows immediate cancellation of pending lock command upon unlock press. |
| Medical Instrumentation | Test & Measurement Equipment |
|
Use Scenario: Controlling LED flash duration in portable pulse oximeters with adjustable exposure time. IC Role / Device Role / Timing Role: One channel sets LED ON time; second channel gates photodiode sampling window - both synchronized to same trigger source. Use Value: External REXT/CEXT tuning enables precise calibration of optical measurement windows; 1.8 V operation extends battery life. |
Use Scenario: Generating calibrated delay pulses for time-domain reflectometry (TDR) stimulus in handheld cable testers. IC Role / Device Role / Timing Role: Monostable produces repeatable, jitter-free trigger pulses with sub-100 ns resolution; retriggering adjusts pulse train density. Use Value: Propagation delay variation < ±5 ns over temperature ensures measurement repeatability; TSSOP16 footprint fits compact handheld form factors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC123APW,118 | Higher speed (tPD = 11 ns typ at VCC = 3.3 V), but narrower VCC range (1.65–3.6 V); no 5 V tolerance. | Preferred for 3.3 V-only high-speed digital systems where 5 V compatibility is unnecessary. | Select when maximum timing precision is required and supply is strictly 3.3 V; avoid if 5 V interface or ultra-low-voltage (1.0–1.2 V) operation needed. |
| SN74LV123AD | SO16 package (SOT109-1); identical electrical specs but larger footprint and higher thermal resistance (12.4 mW/K derating above 110 °C). | Better suited for prototyping or legacy designs requiring through-hole or SOIC-compatible layout. | Choose for manual assembly, breadboarding, or thermal environments below 110 °C where TSSOP thermal limits may be exceeded. |
Compared with 74LV123PW,118, the LVC variant trades 5 V tolerance and 1.0 V operation for speed, while the SN74LV123AD offers identical functionality in a thermally less efficient but more manufacturable package - making the PW version optimal for compact, wide-voltage, production-grade designs.
Availability
74LV123PW,118 is available at Aetrix Electronics and suitable for industrial motor control, automotive body electronics, medical instrumentation, and test & measurement equipment requiring stable component supply across extended temperature ranges and mixed-voltage interfaces.
Supply support for 74LV123PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and discrete components optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.
The 74LV123 belongs to Nexperia's LV logic family, designed specifically for low-voltage, high-noise-immunity timing functions in space-constrained and thermally demanding embedded systems.
FAQ
What is the minimum external capacitor value for stable operation?
The 74LV123PW,118 does not specify a minimum CEXT value; however, for predictable timing accuracy, CEXT ≥ 100 pF is recommended. At very low values (<10 pF), parasitic capacitance dominates, causing pulse width deviation. The device datasheet confirms CEXT has "no limits" and validates operation down to 0 pF (with REXT = 5 kΩ yielding ~70 ns pulse width at VCC = 5.5 V).
Can both monostable channels be triggered simultaneously from a single input signal?
Yes - connecting the same edge-triggered signal to both 1A/1B and 2A/2B inputs (with appropriate polarity matching) allows synchronous triggering of both channels. The functional diagram and truth table confirm independent operation per channel, and no internal crosstalk is specified. Ensure fan-out and drive strength (e.g., microcontroller GPIO) meet combined input capacitance (7 pF per channel) and VIH/VIL thresholds.
How does the reset input interact with an ongoing retriggered pulse?
The nRD input operates asynchronously and immediately forces nQ = LOW and nQ = HIGH on a LOW-going edge, terminating any active pulse regardless of retrigger state or timing component values. This behavior is confirmed in Table 3 (Function Table) and Fig. 11, where nRD overrides all trigger conditions - essential for fail-safe system shutdown or emergency interrupt handling.
Is the TSSOP16 package suitable for reflow soldering in high-volume production?
Yes - the SOT403-1 (TSSOP16) package is qualified for standard lead-free reflow profiles (J-STD-020), with peak temperature rating up to 260 °C. Nexperia specifies moisture sensitivity level (MSL) 1 for this variant, meaning unlimited floor life at ≤30 °C/60 % RH. Its 0.65 mm pitch and exposed pad-free construction ensure reliable automated assembly without bridging or tombstoning.
74LV123PW,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LV
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 14 ns
- Current - Output High, Low:
- 12mA, 12mA
- Voltage - Supply:
- 1 V ~ 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
74LV123PW,118 FAQ
1.How can I place an order for 74LV123PW,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LV123PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LV123PW,118 reliable?
The price and inventory of 74LV123PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV123PW,118 is usually 5 days.
3.What payment methods are accepted for 74LV123PW,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV123PW,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LV123PW,118?
74LV123PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LV123PW,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LV123PW,118?
For technical support, including 74LV123PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV123PW,118 requirements.
6.How does Aetrix verify that 74LV123PW,118 is sourced from the original manufacturer or authorized distributors?
All 74LV123PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV123PW,118 meets industry standards.
7.What is the process for return or replacement of 74LV123PW,118?
All 74LV123PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV123PW,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV123PW,118 part is unused and in its original packaging.
Return procedure for 74LV123PW,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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