Nexperia USA Inc. 74LV138DB,118
- Part No.:
- 74LV138DB,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74LV138DB,118.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,438
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Product details
Overview
74LV138DB,118 from Nexperia is a 3-to-8 line inverting decoder/demultiplexer with three binary address inputs (A0–A2), eight active-LOW mutually exclusive outputs (Y0–Y7), and three enable inputs (E1, E2 active LOW; E3 active HIGH). It operates across 1.0 V to 5.5 V supply range, supports -40 °C to +125 °C ambient, and enables parallel expansion to 1-of-32 decoding using four ICs and one inverter. It is widely used for memory chip select decoding in industrial microcontroller systems.
For engineers reviewing the 74LV138DB,118 datasheet, 74LV138DB,118 pinout, 74LV138DB,118 application, or 74LV138DB,118 equivalent, this page delivers verified functional behavior, SO16 package mapping, propagation delay specs at multiple VCC levels, enable logic truth table, and real-world demultiplexing use cases - all confirmed against Nexperia's Rev. 7 product data sheet dated 23 January 2024.
Technical Context
The 74LV138DB,118 implements combinational logic decoding with strict mutual exclusivity: only one output goes LOW when all enables are satisfied (E1 = E2 = LOW, E3 = HIGH) and a unique A2:A0 combination is applied. Its enable architecture allows cascading without external logic - E1/E2 serve as group selects while E3 acts as global strobe, enabling hierarchical decoding trees.
Input clamping diodes permit safe interfacing to voltages exceeding VCC when current-limiting resistors are used. Output drive capability is specified at ±6 mA (VCC = 3.0 V) and ±12 mA (VCC = 4.5 V), with guaranteed VOL ≤ 0.40 V and VOH ≥ 2.4 V under those loads - ensuring reliable TTL and CMOS level compatibility across its full 1.0–5.5 V operating range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.0 V to 5.5 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| Propagation Delay (tpd) | 12 ns typical at VCC = 3.3 V, CL = 15 pF - enables reliable operation in sub-50 MHz address decode paths. |
| Output Drive Strength | ±6 mA at VCC = 3.0 V - sufficient to drive 10+ 74LVC inputs or small LED loads via external pull-ups. |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood industrial control, motor drives, and power supply management systems. |
| Power Dissipation | 500 mW max at Tamb ≤ 110 °C (SO16 package) - derates linearly above 110 °C (12.4 mW/K), supporting thermal-aware board layout. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - exceeds JEDEC JS-001/JS-002 Class 2/C3, reducing handling sensitivity in automated assembly. |
| Input Transition Rate | Min 50 ns/V at VCC = 5.5 V - ensures robust timing margin against fast-edge noise in mixed-signal PCBs. |
Pinout & Package
74LV138DB,118 is supplied in SO16 (SOT109-1) plastic small outline package: 16-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, RoHS-compliant. Pin 1 index located at top-left corner with notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3 | A0, A1, A2 | Binary address inputs - define which of eight outputs (Y0–Y7) activates LOW; decoded in standard 3-bit weighted order. |
| 4, 5 | E1, E2 | Active-LOW enable inputs - both must be LOW for any output to respond; used for hierarchical decoding and chip select grouping. |
| 6 | E3 | Active-HIGH enable input - functions as global strobe; enables full decoder operation only when HIGH. |
| 7, 9–15 | Y0, Y7, Y5, Y4, Y3, Y2, Y1, Y6 | Active-LOW decoded outputs - exactly one output goes LOW per valid address/enable combination; others remain HIGH. |
| 8 | GND | Ground reference - must be low-impedance connection; shared return path for all internal logic and output switching currents. |
| 16 | VCC | Positive supply - powers all internal CMOS circuitry; decoupling capacitor (100 nF) required within 5 mm of this pin. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (1.0–5.5 V) | Eliminates need for separate voltage translators when interfacing with mixed-supply SoCs, FPGAs, or legacy 5 V peripherals. |
| Inverting active-LOW outputs | Directly drives common-cathode LED arrays, N-channel MOSFET gates, or enables /CS lines on SRAM/Flash without inverters. |
| Multiple enable architecture (E1, E2, E3) | Enables 1-of-32 expansion using only four 74LV138s and one inverter - no additional glue logic required. |
| Clamp diode-equipped inputs | Permits safe connection to 12 V or 24 V control signals via series current-limiting resistors, simplifying industrial I/O design. |
| Latch-up immunity > 100 mA | Meets JESD78 Class II Level B - prevents destructive latch-up during transient overvoltage events in noisy environments. |
Applications
| Memory Address Decoding | Industrial I/O Expansion |
|---|---|
|
Use Scenario: Selecting one of eight SRAM or Flash memory chips in a microcontroller-based data logger. IC Role / Device Role / Timing Role: Acts as address-space partitioner - converts upper address bits into individual /CE signals with <12 ns propagation delay. Use Value: Reduces FPGA or MCU GPIO count by 8×; eliminates software-based chip select delays and improves deterministic access timing. |
Use Scenario: Expanding discrete digital outputs from a PLC CPU to control 8 solenoid valves in a packaging machine. IC Role / Device Role / Timing Role: Functions as demultiplexer - E3 accepts serial control pulse, A0–A2 select valve index, outputs drive optocoupler inputs. Use Value: Enables single-wire command bus with precise per-valve activation timing; avoids timing skew from software polling loops. |
| LED Segment Selection | Test Equipment Signal Routing |
|
Use Scenario: Driving common-anode 7-segment displays in a multi-channel power meter front panel. IC Role / Device Role / Timing Role: Serves as digit selector - outputs sink current from segment drivers; E1/E2 manage display bank selection. Use Value: Supports multiplexed display update at >1 kHz without flicker; leverages active-LOW outputs to directly interface with PNP segment drivers. |
Use Scenario: Routing test signals between DUT and measurement instruments in an automated functional tester. IC Role / Device Role / Timing Role: Configured as 1-of-8 signal path selector - E3 acts as test mode enable, A0–A2 choose channel, outputs gate analog switches. Use Value: Provides glitch-free, low-capacitance (<3.5 pF input) signal routing with sub-15 ns switching - critical for high-fidelity analog stimulus/response capture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC138PW,118 | Lower propagation delay (9 ns typ. @ 3.3 V), but narrower VCC range (1.65–3.6 V); no 5 V tolerance. | Not suitable for mixed 5 V/3.3 V systems; requires level-shifting if interfacing with 5 V controllers. | Select when speed is critical and supply is strictly 3.3 V or lower; avoid in legacy 5 V designs. |
| SN74HC138PWR | Higher VCC min (2 V), slower tpd (22 ns @ 5 V), higher ICC (80 μA vs. 20 μA), no 1.2 V operation. | Cannot operate below 2 V - incompatible with ultra-low-power 1.8 V or 1.2 V SoCs. | Choose only for cost-sensitive 5 V-only applications where LV performance and wide VCC are unnecessary. |
Compared with 74LV138DB,118, the 74LVC138PW,118 trades supply flexibility for speed, while SN74HC138PWR sacrifices low-voltage operation and static power for broader legacy 5 V compatibility - making the 74LV138DB,118 uniquely balanced for modern mixed-voltage embedded systems requiring both robustness and efficiency.
Availability
74LV138DB,118 is available at Aetrix Electronics and suitable for industrial control panels, programmable logic controllers, and embedded data acquisition systems requiring stable component supply across extended temperature ranges and mixed-voltage interfaces.
Supply support for 74LV138DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading Dutch semiconductor manufacturer specializing in high-volume, high-reliability logic, analog, and discrete components for industrial, automotive, and consumer markets.
The 74LV logic family was engineered for low-voltage interoperability across heterogeneous system architectures - delivering consistent timing, rail-to-rail compatibility, and robust ESD/latch-up performance from 1.0 V to 5.5 V.
FAQ
Can 74LV138DB,118 operate at 1.2 V supply?
Yes. The device is fully specified down to 1.0 V supply, with guaranteed functionality at 1.2 V including VIH/VIL thresholds, propagation delay (75 ns typ.), and output drive. This enables direct integration with ultra-low-power microcontrollers and energy-harvesting systems without voltage translation.
What is the maximum clock/data rate supported for demultiplexing?
While not a clocked device, its propagation delay of 12 ns (typ.) at 3.3 V implies reliable operation with address/control edges up to ~40 MHz. For clean demux operation, input transition rates should exceed 50 ns/V per datasheet Table 5 - limiting minimum edge rate to 165 ns at 3.3 V.
How does the enable logic work when expanding to 1-of-32 decoding?
E1 and E2 act as MSB group selects: two bits choose one of four 74LV138s, while E3 of each IC is driven by the inverted LSB pair from a fifth decoder. This yields 32 unique outputs with zero external logic beyond one inverter - confirmed in Section 1 of the datasheet.
Is thermal pad on the DHVQFN variant present on the SO16 package?
No. The SO16 (SOT109-1) package has no thermal pad. Thermal management relies on copper pour under pins 7–8 and 15–16, plus trace width optimization. The DHVQFN16 (SOT763-1) variant includes an exposed thermal pad, but 74LV138DB,118 uses SO16 - confirmed by ordering code "DB" and Table 1.
74LV138DB,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LV
- Package/Case:
- 16-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 12mA, 12mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
74LV138DB,118 FAQ
1.How can I place an order for 74LV138DB,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LV138DB,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LV138DB,118 reliable?
The price and inventory of 74LV138DB,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV138DB,118 is usually 5 days.
3.What payment methods are accepted for 74LV138DB,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV138DB,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LV138DB,118?
74LV138DB,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LV138DB,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LV138DB,118?
For technical support, including 74LV138DB,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV138DB,118 requirements.
6.How does Aetrix verify that 74LV138DB,118 is sourced from the original manufacturer or authorized distributors?
All 74LV138DB,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV138DB,118 meets industry standards.
7.What is the process for return or replacement of 74LV138DB,118?
All 74LV138DB,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV138DB,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV138DB,118 part is unused and in its original packaging.
Return procedure for 74LV138DB,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LV138DB,118 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
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