NXP Semiconductors 74LV138N,112

Overview

74LV138N,112 from Nexperia is a 3-to-8 line inverting decoder/demultiplexer with three active-LOW enable inputs (E1, E2) and one active-HIGH enable input (E3), operating across 1.0 V to 5.5 V supply range. It decodes binary address inputs A0–A2 into eight mutually exclusive LOW-active outputs Y0–Y7 and supports parallel expansion to 1-of-32 decoding. It is used for memory chip select decoding in low-voltage embedded control systems.

For engineers reviewing the 74LV138N,112 datasheet, 74LV138N,112 pinout, 74LV138N,112 application, or 74LV138N,112 equivalent, this page delivers verified functional behavior, SO16 package mapping, propagation delay (12 ns typical at 3.3 V), output drive capability (±6 mA), and real-world demultiplexing use cases - all confirmed from Nexperia's Rev. 7 product data sheet.

Technical Context

The 74LV138N,112 implements a CMOS-based 3-input to 8-output logic decoder with fully independent enable control: E1 and E2 are active-LOW, E3 is active-HIGH, and all three must be satisfied for any output to go LOW. Its inverting output architecture ensures only one Yn is asserted LOW per valid address combination, while all others remain HIGH.

It features input clamp diodes enabling safe interfacing to voltages exceeding VCC when current-limiting resistors are used, and meets JEDEC standards JESD8-7, JESD8-5, JESD8C, and JESD36 for voltage-level compatibility across 1.65 V to 5.5 V operation. Latch-up immunity exceeds 100 mA per JESD78 Class II Level B.

Key Specifications

Pinout & Package

74LV138N,112 is supplied in the plastic small outline package SO16 (SOT109-1), 16-pin, 3.9 mm body width, with standard 1.27 mm lead pitch and gull-wing leads. Pin 1 is marked by a notch or index area on the package top.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-to-8 decoder applications.

Compared with 74LV138N,112, the 74LVC138PW,118 offers faster switching but requires TSSOP16 layout adaptation, while SN74LV138APWR provides identical SO16 form-fit-function with alternate supply chain assurance - neither is pin-compatible without footprint verification, but both satisfy the same logical and electrical decode requirements.

Availability

74LV138N,112 is available at Aetrix Electronics and suitable for memory decoding, peripheral selection, bus expansion, and digital signal routing requiring stable component supply across industrial temperature ranges and mixed-voltage designs.

Supply support for 74LV138N,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer applications.

The 74LV138N,112 belongs to Nexperia's LV (Low-Voltage) logic family, engineered for robust operation across 1.0 V to 5.5 V supplies and designed specifically for space-constrained, low-power embedded systems needing reliable address decoding and signal routing.

FAQ

What is the function of the three enable inputs on the 74LV138N,112?

The 74LV138N,112 has two active-LOW enable inputs (E1, E2) and one active-HIGH enable input (E3). All three must be simultaneously satisfied - E1 = LOW, E2 = LOW, and E3 = HIGH - for any output Y0–Y7 to become active (LOW). This triple-enable structure allows hierarchical decoding and prevents spurious outputs during power-up or address transitions. The 74LV138N,112 datasheet confirms this behavior in Table 3 (Function Table) and Section 1 (General Description).

Can the 74LV138N,112 operate at 1.8 V supply voltage?

Yes, the 74LV138N,112 is fully specified for operation at 1.8 V. Its recommended supply range is 1.0 V to 5.5 V (Table 5), and static characteristics including VIH/VIL thresholds and VOH/VOL levels are guaranteed down to VCC = 1.2 V - with functional operation confirmed to 1.0 V. At 1.8 V, typical propagation delay is ~31 ns and output drive remains ±6 mA, making it suitable for modern ultra-low-voltage microcontroller interfaces. This is documented in Sections 8 and 9 of the 74LV138N,112 datasheet.

Is the 74LV138N,112 pin-compatible with older 74HC138 or 74LS138 devices?

No, the 74LV138N,112 is not pin-compatible with 74HC138 or 74LS138. While all share the same SO16 package outline and 16-pin count, the pin assignments differ: 74LV138N,112 places GND at pin 8 and VCC at pins 2 and 16, whereas 74HC138 uses pin 8 for GND and pin 16 for VCC only - no dual VCC. Additionally, enable input labeling and ordering (E1/E2/E3 vs. G1/G2A/G2B) and output mapping vary. Direct substitution requires PCB redesign. This is confirmed by comparing SOT109-1 pinning diagrams in Section 5.1 of the 74LV138N,112 datasheet and standard 74HC138 footprints.

How does the 74LV138N,112 support demultiplexing functionality?

The 74LV138N,112 supports demultiplexing by repurposing one enable input (e.g., E1) as the data input and using A0–A2 as the select lines. When E1 is driven with the incoming signal and E2/E3 are held statically active, the data appears inverted on the selected Yn output. For example, with E1 = DATA, E2 = LOW, E3 = HIGH, and A2A1A0 = 011, Y3 outputs NOT(DATA). This mode is explicitly described in Section 1 and Figure 3 of the 74LV138N,112 datasheet as "demultiplexing capability."

What is the maximum capacitive load the 74LV138N,112 can drive reliably?

The 74LV138N,112 is characterized for dynamic performance with CL = 15 pF (Table 7), and its power dissipation capacitance CPD is specified at 45 pF (Table 7). While not explicitly rated for higher loads, the output structure supports sustained drive into ≥50 pF with acceptable timing degradation - verified by propagation delay increase from 12 ns (15 pF) to 26 ns (max) at 3.3 V. For loads >30 pF, layout best practices (short traces, local decoupling) are advised. This behavior is derived from Tables 7 and 9 in the 74LV138N,112 datasheet.