NXP Semiconductors 74LV153D,118

Overview

74LV153D,118 from NXP Semiconductors is a low-voltage CMOS dual 4-input multiplexer with independent active-LOW enable inputs (1E, 2E), common select inputs (S0, S1), non-inverting outputs (1Y, 2Y), and operation across 1.0 V to 3.6 V supply. It implements two independent 2-pole, 4-position logic switches for data routing in register banks or function generation in irregular combinational logic.

For engineers reviewing the 74LV153D,118 datasheet, 74LV153D,118 pinout, 74LV153D,118 application, or 74LV153D,118 equivalent, key selection criteria include its 16-pin SO16 package, −40 °C to +125 °C temperature range, 14 ns propagation delay at 3.3 V/15 pF, TTL-level input compatibility at V_CC ≥ 2.7 V, and ESD robustness (HBM > 2000 V).

Technical Context

The 74LV153D,118 integrates two identical 4:1 multiplexer channels sharing S0 and S1 select lines but featuring separate output enables (1E, 2E) and outputs (1Y, 2Y). Each channel selects one of four data inputs (1I0–1I3 or 2I0–2I3) based on binary S1S0 state, with output disabled (forced LOW) when its enable is HIGH.

Its Si-gate CMOS architecture ensures rail-to-rail output swing, low static current (≤160 μA at 3.6 V), and compatibility with both LV and legacy TTL logic families. Propagation delays are specified per path: data input to output (1In→1Y), select input to output (S0/S1→1Y), and enable input to output (1E→1Y), with worst-case t_pd = 39 ns at 3.6 V over full temperature range.

Key Specifications

Pinout & Package

74LV153D,118 is housed in a plastic small outline package (SO16) with 16 leads, 3.9 mm body width, and standard JEDEC MS-012 footprint (SOT109-1). Pin 1 is marked by a notch or bevel; device orientation follows conventional IC marking convention with pin 1 at top-left corner when viewed from top with marking side up.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 4-input multiplexer applications.

Compared with 74LV153D,118, the 74HC153D,653 trades low-voltage operation for higher noise margins at 5 V, while the SN74LV153APWR offers identical functionality in a smaller TSSOP package-neither is pin-compatible without layout revision, but both serve overlapping data-routing roles in industrial and test equipment.

Availability

74LV153D,118 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, embedded microcontroller data bus switching, programmable logic function generation, and digital test equipment signal routing requiring stable component supply across extended temperature ranges.

Supply support for 74LV153D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.

The 74LV153D,118 belongs to NXP's 74LV logic family, designed specifically for low-voltage, high-noise-immunity digital interfacing in industrial automation, test instrumentation, and embedded control systems operating from 1.0 V to 3.6 V.

FAQ

What is the maximum supply voltage for 74LV153D,118?

The absolute maximum supply voltage for 74LV153D,118 is +4.6 V, but the recommended operating range is 1.0 V to 3.6 V. Operation above 3.6 V risks permanent damage per IEC 60134 limiting values, and functional guarantees apply only within the 1.0–3.6 V band. At 3.6 V, ICC remains ≤160 μA, confirming safe steady-state operation.

Does 74LV153D,118 support TTL-level inputs?

Yes, 74LV153D,118 accepts TTL input levels when V_CC is between 2.7 V and 3.6 V - VIH ≥ 2.0 V and VIL ≤ 0.8 V meet standard TTL thresholds. This allows direct connection to 74LS or 74F outputs without level-shifting circuitry, simplifying upgrades from legacy 5 V systems to 3.3 V logic domains.

What is the propagation delay of 74LV153D,118 at 3.3 V?

At V_CC = 3.3 V with 15 pF load, the typical propagation delay (t_pd) of 74LV153D,118 is 14 ns for data input-to-output (1In→1Y) and select input-to-output (S0/S1→1Y) paths. The worst-case delay over −40 °C to +125 °C is 33 ns, ensuring timing predictability in thermally demanding industrial environments.

Can 74LV153D,118 be used in cascaded multiplexer configurations?

Yes, 74LV153D,118 supports cascading via its individual active-LOW enable inputs (1E, 2E). One 74LV153D,118 can enable/disable another's outputs to build larger multiplexers (e.g., 8:1 or 16:1), eliminating need for external AND gates. The function table confirms nY = L when nE = H, enabling clean hierarchical control without signal contention.

What package type is used for 74LV153D,118?

74LV153D,118 uses the SO16 plastic small outline package (SOT109-1) with 16 leads and 3.9 mm body width. Its JEDEC MS-012 footprint is compatible with standard surface-mount assembly processes, and thermal resistance (R_θJA) is rated for 500 mW max power dissipation in still air - verified per NXP's Rev. 5 datasheet.