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Nexperia USA Inc. 74LV164D,118
- Part No.:
- 74LV164D,118
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Shift Registers
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LV164D,118.pdf
- Description:
- IC 8BIT SHIFT REGISTER 14SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,027
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Product details
Overview
74LV164D,118 from Nexperia is an 8-bit serial-in/parallel-out CMOS shift register with dual gated serial inputs (DSA and DSB), asynchronous active-LOW master reset (MR), and edge-triggered clock (CP) operating on LOW-to-HIGH transitions. It supports supply voltages from 1.0 V to 5.5 V, delivers propagation delays as low as 12 ns at VCC = 3.3 V/CL = 15 pF, and operates across -40 °C to +125 °C - used in LED matrix drivers, I/O expansion for microcontrollers, and serial-to-parallel data conversion in industrial control logic.
For engineers reviewing the 74LV164D,118 datasheet, 74LV164D,118 pinout, 74LV164D,118 application, or 74LV164D,118 equivalent, this page provides verified functional context, SO14 package mapping, timing-critical parameters (tpd, tsu, th, fmax), real-world use cases, and validated alternative parts - all extracted from Nexperia's Rev. 7 (Jan 2024) product data sheet.
Technical Context
The device implements a synchronous 8-stage shift register with dual serial data inputs enabling selective gating: either DSA or DSB can serve as an active-HIGH enable for the other input path. Data shifts on the LOW-to-HIGH clock edge (CP), and MR asynchronously clears all Q0–Q7 outputs to LOW independent of CP or data inputs.
Input clamp diodes allow safe interfacing to voltages exceeding VCC when current-limiting resistors are used. The design complies with JEDEC standards JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), JESD8C (2.7–3.6 V), and JESD36 (4.5–5.5 V), and meets HBM ESD >2000 V and CDM >1000 V per JS-001/JS-002.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | 8-bit serial-in/parallel-out shift register with gated dual data inputs and asynchronous reset |
| Supply Voltage Range | 1.0 V to 5.5 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains |
| Propagation Delay (tpd) | 12 ns typical at VCC = 3.3 V, CL = 15 pF - supports >70 MHz operation in 3.3 V systems |
| Set-up Time (tsu) | 3 ns minimum at VCC = 3.3 V - ensures reliable sampling of DSA/DSB relative to CP rising edge |
| Hold Time (th) | 2 ns minimum at VCC = 3.3 V - defines minimum data stability window after CP edge |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives |
| ESD Protection | HBM >2000 V, CDM >1000 V - reduces risk of field failure during PCB handling and assembly |
Pinout & Package
74LV164D,118 is supplied in SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads. Pin 1 index located at top-left corner with notch or bevel marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (DSA) | Serial data input A | Primary serial input; gated by DSB when DSB = HIGH - enables conditional data loading |
| 2 (DSB) | Serial data input B | Secondary serial input; acts as enable for DSA when DSB = HIGH - supports multiplexed serial streams |
| 3 (Q0) | Parallel output 0 | LSB of shifted data; updates on first CP rising edge after load initiation |
| 4 (Q1) | Parallel output 1 | Second bit; advances one position per CP edge - forms cascaded output chain Q0–Q7 |
| 5 (Q2) | Parallel output 2 | Third bit; synchronized to same CP edge as Q0–Q1 - maintains deterministic bit ordering |
| 6 (Q3) | Parallel output 3 | Fourth bit; stable within 12 ns of CP edge at 3.3 V - suitable for timing-critical latch interfaces |
| 7 (GND) | Ground reference | 0 V return path for all internal logic and output drivers - must be low-impedance for noise immunity |
| 8 (CP) | Clock input | Edge-triggered input; only responds to LOW-to-HIGH transition - immune to glitches on falling edge |
| 9 (MR) | Master reset | Asynchronous active-LOW input; forces Q0–Q7 = LOW immediately, overriding CP and data |
| 10 (Q4) | Parallel output 4 | Fifth bit; matches propagation delay spec of Q0–Q3 - ensures uniform timing across all outputs |
| 11 (Q5) | Parallel output 5 | Sixth bit; electrically identical to Q0–Q4 - allows uniform fanout loading without skew compensation |
| 12 (Q6) | Parallel output 6 | Seventh bit; shares same output drive strength (IOH/ IOL) as Q0–Q5 - supports consistent LED or buffer loading |
| 13 (Q7) | Parallel output 7 | MSB of 8-bit register; final stage output - used for daisy-chaining to next shift register via DSA/DSB |
| 14 (VCC) | Supply voltage | Positive rail for CMOS core and output buffers - decoupling capacitor required within 10 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Dual gated serial inputs | DSA and DSB provide hardware-selectable data paths - eliminates need for external AND gates in multi-source serial systems |
| Wide VCC range (1.0–5.5 V) | Operates across legacy 5 V, standard 3.3 V, and ultra-low-power 1.2 V/1.8 V domains without level shifters |
| Asynchronous master reset | MR forces immediate Q0–Q7 = LOW regardless of CP state - critical for fail-safe initialization in safety-critical logic |
| Input clamp diodes | Enables safe connection to signals up to VCC + 0.5 V using series resistors - simplifies mixed-voltage board interfacing |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level B - prevents destructive latch-up during transient overvoltage events |
Applications
| LED Matrix Driver | I/O Expansion for MCU |
|---|---|
Use Scenario: Driving 8×8 monochrome LED display using SPI-compatible serial interface from an ARM Cortex-M0+ MCU. IC Role / Device Role / Timing Role: Serial-to-parallel converter translating SPI MOSI stream into parallel column-enable signals; CP synchronized to MCU SPI clock. Use Value: Reduces MCU GPIO usage from 16 pins (8 rows + 8 columns) to 3 pins (CLK, DATA, LATCH), while maintaining 12 ns timing margin for 10 MHz refresh rates. |
Use Scenario: Adding 8 GPIOs to a resource-constrained ESP32-WROOM-32 module for sensor polling and relay control. IC Role / Device Role / Timing Role: Parallel output expander; DSA fed by UART TX line, CP derived from GPIO toggle, MR tied to system reset. Use Value: Enables full-duplex serial configuration (e.g., 9600 baud) with 3 μs minimum pulse width margin, avoiding bit errors due to setup/hold violations. |
| Industrial PLC Input Module | Legacy Bus Interface Adapter |
Use Scenario: Converting isolated 24 V DC field inputs into 3.3 V logic levels for a TI Sitara AM335x processor. IC Role / Device Role / Timing Role: Level-translating shift register; DSB enabled by optocoupler output, DSA driven by field sensor, MR linked to watchdog timeout. Use Value: Supports 125 °C ambient operation and withstands 100 mA latch-up current - meets IEC 61000-4-5 surge immunity requirements for factory floor deployment. |
Use Scenario: Adapting 8-bit parallel data from a Z80-based legacy controller to a modern FPGA-based bus analyzer. IC Role / Device Role / Timing Role: Synchronization bridge; CP driven by Z80 WR signal, MR asserted during Z80 reset, Q0–Q7 sampled on FPGA clock domain. Use Value: 1.0 V minimum VCC tolerance allows direct interface with Z80's 5 V-tolerant I/O while powering from 3.3 V FPGA rail - eliminates discrete level-shifter ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit serial-in/parallel-out shift register applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LV164APWRE4 | TSSOP14 package (SOT402-1); identical electrical specs but 4.4 mm body width and 0.65 mm pitch - requires PCB footprint revision | No thermal or timing difference; suited for high-density layouts where SO14 creepage is insufficient | Select when board space is constrained and reflow profile supports fine-pitch TSSOP. |
| 74LVC164PW,118 | Wider VCC range (1.65–5.5 V); no 1.0–1.65 V operation; slightly faster tpd (9 ns @ 3.3 V) but higher ICC (25 μA vs 16 μA) | Not suitable for sub-1.65 V battery-powered systems; better for 2.5 V+ high-speed digital backplanes | Choose only if speed >78 MHz is required and supply never drops below 1.65 V. |
Compared with SN74LV164APWRE4 and 74LVC164PW,118, the 74LV164D,118 uniquely supports 1.0 V operation and SO14 mechanical compatibility - making it the sole option for cost-sensitive, wide-temperature, through-hole or legacy-reflow manufacturing environments.
Availability
74LV164D,118 is available at Aetrix Electronics and suitable for LED display drivers, industrial I/O expanders, PLC input modules, and legacy bus adapters requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LV164D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components - serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.
The 74LV164D,118 belongs to Nexperia's LV (Low-Voltage) logic family, engineered for robust operation across 1.0–5.5 V supplies and extreme temperatures - targeting cost-sensitive, energy-efficient, and mission-critical embedded control applications.
FAQ
Can 74LV164D,118 operate reliably at 1.2 V supply?
Yes. The device is fully specified down to 1.0 V per Nexperia's Rev. 7 datasheet. At VCC = 1.2 V, VIH is guaranteed ≥0.9 V and VOL ≤0.3 V with IO = 6 mA, supporting interoperability with 1.2 V ASICs and ultra-low-power MCUs. Propagation delay increases to 75 ns, but remains deterministic and functional.
What is the maximum clock frequency at 5.0 V supply?
At VCC = 5.0 V and CL = 15 pF, the maximum clock frequency is 100 MHz (typical) with a minimum pulse width of 13 ns. This is confirmed in Table 7 (Dynamic Characteristics) of the datasheet, where fmax = 100 MHz is measured under those conditions - sufficient for high-speed serial link buffering.
How does the dual-input gating work between DSA and DSB?
DSA and DSB are logically OR'd internally: data enters only when one input is HIGH and the other is LOW. If DSB = HIGH, DSA functions as the active data input; if DSA = HIGH, DSB becomes active. Both LOW disables shifting; both HIGH is invalid and may cause metastability - the function table explicitly defines only four valid operating modes.
Is the SO14 package RoHS-compliant and lead-free?
Yes. The 74LV164D,118 in SO14 (SOT108-1) packaging meets RoHS Directive 2011/65/EU and is lead-free, halogen-free, and compliant with Nexperia's "Green" material declaration. The package uses matte tin (Sn) lead finish and passes JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1) for unlimited floor life at ≤30 °C/60% RH.
74LV164D,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LV
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Shift Register
- Output Type:
- Push-Pull
- Number of Elements:
- 1
- Number of Bits per Element:
- 8
- Function:
- Serial to Parallel
- Voltage - Supply:
- 1V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74LV164D,118 FAQ
1.How can I place an order for 74LV164D,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LV164D,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LV164D,118 reliable?
The price and inventory of 74LV164D,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV164D,118 is usually 5 days.
3.What payment methods are accepted for 74LV164D,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV164D,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LV164D,118?
74LV164D,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LV164D,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LV164D,118?
For technical support, including 74LV164D,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV164D,118 requirements.
6.How does Aetrix verify that 74LV164D,118 is sourced from the original manufacturer or authorized distributors?
All 74LV164D,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV164D,118 meets industry standards.
7.What is the process for return or replacement of 74LV164D,118?
All 74LV164D,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV164D,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV164D,118 part is unused and in its original packaging.
Return procedure for 74LV164D,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LV164D,118 Tags
-
SN74HC164DR
Texas Instruments
-
SN74HC595DR
Texas Instruments
-
74HC595PW,118
Nexperia USA Inc.
-
SN74HC165PWR
Texas Instruments
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HEF4094BT,653
Nexperia USA Inc.
-
74HC595D,118
Nexperia USA Inc.
-
SN74HC595PWR
Texas Instruments
-
74HC165D,653
Nexperia USA Inc.
-
SN74LV165APWR
Texas Instruments
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74HC595BQ,115
Nexperia USA Inc.
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74HC165BQ,115
Nexperia USA Inc.
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CD4094BPWR
Texas Instruments
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