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Home > Products > Integrated Circuits (ICs) > Logic > Shift Registers

Nexperia USA Inc. 74LV164PW,118

Name: 74LV164PW,118
Brand: Nexperia USA Inc.
SKU: 74LV164PW,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74LV164PW,118

Manufacturer:: Nexperia USA Inc.

Category:: Shift Registers

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: 74LV164PW,118.pdf

Description:: IC 8BIT SHIFT REGISTER 14TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74LV164PW,118 from Nexperia is an 8-bit serial-in/parallel-out CMOS shift register with dual gated serial inputs (DSA, DSB), asynchronous master reset (MR), and edge-triggered clock (CP). It operates from 1.0 V to 5.5 V, delivers propagation delay as low as 12 ns at VCC = 3.3 V/CL = 15 pF, and supports industrial temperature range (−40 °C to +125 °C). It is used in LED matrix drivers, address expansion for microcontrollers, and serial-to-parallel data conversion in embedded control systems.

For engineers reviewing the 74LV164PW,118 datasheet, 74LV164PW,118 pinout, 74LV164PW,118 application, or 74LV164PW,118 equivalent, key selection criteria include supply voltage flexibility (1.0–5.5 V), dual-input gating logic, guaranteed operation up to 125 °C, and TSSOP14 package compatibility with high-density PCB layouts.

Technical Context

The device implements a synchronous 8-stage shift register with independent serial data enable logic: either DSA or DSB can serve as an active-HIGH gate for the other input, enabling flexible serial data routing. Its CP input triggers on LOW-to-HIGH transitions, and MR forces all Q0–Q7 outputs LOW asynchronously.

Input clamp diodes allow safe interfacing to voltages exceeding VCC when used with current-limiting resistors. The design complies with JEDEC standards JESD8-7, JESD8-5, JESD8C, and JESD36 across its full supply range, and meets HBM ESD > 2000 V and CDM > 1000 V per JS-001/JS-002.

Key Specifications

Parameter	Value and Actual Design Meaning
Function	8-bit serial-in/parallel-out shift register with gated dual data inputs and asynchronous reset
Supply Voltage Range	1.0 V to 5.5 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains
Propagation Delay (t_pd)	12 ns typical at VCC = 3.3 V, CL = 15 pF - supports ≥70 MHz clock rates in 3.3 V systems
Operating Temperature	−40 °C to +125 °C - qualified for extended industrial and under-hood applications
Input Logic Compatibility	TTL-level inputs supported at VCC = 2.7 V to 3.6 V - allows mixed-voltage system integration without level shifters
ESD Robustness	HBM > 2000 V, CDM > 1000 V - reduces susceptibility to handling damage and board-level transients
Power Dissipation	ICC ≤ 160 μA max at VCC = 5.5 V, no load - suitable for battery-powered and low-quiescent-current designs

Pinout & Package

TSSOP14 package (SOT402-1): plastic thin shrink small outline, 14 leads, body width 4.4 mm, 0.65 mm pitch, exposed pad not electrically connected.

Pin/Terminal	Circuit Role	Design Meaning
1 - DSA	Serial data input A	Primary serial input; gated by DSB when DSB = HIGH - enables conditional data loading
2 - DSB	Serial data input B	Secondary serial input; acts as active-HIGH enable for DSA - provides flexible serial control logic
3 - Q0	Parallel output 0	LSB of shifted data; updated on each CP rising edge after reset or shift cycle
4 - Q1	Parallel output 1	Second bit of parallel output bus; synchronized to CP edge and MR state
5 - Q2	Parallel output 2	Third bit; maintains deterministic timing relationship with CP and MR signals
6 - Q3	Parallel output 3	Fourth bit; part of 8-bit contiguous output group Q0–Q7
7 - GND	Ground reference	0 V return path for all internal circuitry and I/O; must be low-impedance for noise immunity
8 - CP	Clock input	Edge-triggered (LOW-to-HIGH); controls shift timing and output update synchronously
9 - MR	Master reset	Asynchronous active-LOW signal; clears all outputs to LOW regardless of CP or data state
10 - Q4	Parallel output 4	Fifth bit; shares same timing and drive strength characteristics as Q0–Q3
11 - Q5	Parallel output 5	Sixth bit; designed for consistent fan-out and capacitive loading behavior
12 - Q6	Parallel output 6	Seventh bit; supports simultaneous 8-bit parallel readout after serial load completion
13 - Q7	Parallel output 7	MSB of parallel output; completes full 8-bit data word; matches Q0–Q6 electrical specs
14 - VCC	Supply voltage	Positive rail for core and I/O; powers internal logic and output drivers; decoupling required near pin

Key Features

Feature	Design Value
Dual gated serial inputs	DSA and DSB provide hardware-selectable data path control without external logic or software overhead
Wide voltage operation	1.0 V to 5.5 V supply range enables single-device support across multiple logic families and power domains
Asynchronous master reset	MR asserts independently of clock, ensuring deterministic initialization in safety-critical or startup-sensitive circuits
Clamp diode protected inputs	Integrated input diodes allow safe overvoltage tolerance when used with series resistors - eliminates need for external protection
High-temperature qualification	Guaranteed operation to +125 °C supports deployment in automotive engine control, industrial motor drives, and outdoor equipment

Applications

LED Display Driver

Microcontroller I/O Expansion

Use Scenario: Driving 8-segment or 8×8 LED matrices where serial data from MCU must be converted to parallel column/row activation signals.

IC Role / Device Role: Serial-to-parallel data converter that buffers and latches incoming bitstream into stable 8-bit parallel outputs for direct LED sink/source control.

Use Value: Reduces MCU GPIO usage by 7 pins versus direct parallel connection; supports daisy-chaining for larger displays via Q7 cascade.

Use Scenario: Expanding limited GPIO count on low-pin-count MCUs (e.g., ARM Cortex-M0+, PIC16) to interface with multiple peripherals or sensors.

IC Role / Device Role: Parallel output latch that accepts serial configuration commands and holds static I/O states until next update cycle.

Use Value: Enables 8 additional digital outputs using only 2 MCU pins (CP + DSA/DSB); MR allows synchronized reset of all expanded I/Os.

Industrial Control Bus Interface

Legacy System Protocol Translation

Use Scenario: Converting serial command streams from PLCs or fieldbus masters into parallel control bits for relay banks, solenoid drivers, or status indicators.

IC Role / Device Role: Synchronous shift register acting as protocol bridge between serial control layer and parallel actuator interface layer.

Use Value: Provides deterministic timing (12 ns t_pd at 3.3 V) and robust noise immunity (clamped inputs, 125 °C rating) in electrically noisy factory environments.

Use Scenario: Adapting older 8-bit parallel peripheral interfaces (e.g., printers, modems) to modern serial-only SoCs or FPGAs.

IC Role / Device Role: Bidirectional serial/parallel translator that reconstructs legacy parallel handshaking using MR and CP timing coordination.

Use Value: Maintains compatibility with discontinued components while leveraging modern serial interfaces - avoids redesign of entire subsystem.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit serial-in/parallel-out shift register applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LV164APWRE4	TI variant in same TSSOP14 package; identical pinout but slightly higher ICC (max 250 μA vs 160 μA) and wider t_pd range (14–29 ns at 3.3 V)	Valid for drop-in replacement where lower quiescent current is not critical; requires verification of reset timing margin due to longer t_PHL	Select when TI supply chain alignment is required; confirm layout compatibility with thermal pad absence in SN74LV164APWRE4
74HC164PW,118	Nexperia HC version: higher VCC min (2.0 V), faster speed at 5 V (t_pd = 12 ns), but no 1.0–1.8 V operation or 125 °C rating	Only suitable for 4.5–5.5 V systems requiring higher speed; excludes battery-powered or wide-VCC applications	Choose only if operating strictly at 5 V and ambient ≤ 85 °C; avoid for low-voltage or extended-temp designs

Compared with SN74LV164APWRE4 and 74HC164PW,118, the 74LV164PW,118 uniquely supports 1.0 V operation and full −40 °C to +125 °C functionality - making it the sole option for ultra-low-power, wide-temperature embedded systems requiring guaranteed sub-2 V logic compatibility.

Availability

74LV164PW,118 is available at Aetrix Electronics and suitable for LED display drivers, microcontroller I/O expansion, and industrial control bus interfaces requiring stable component supply across extended temperature ranges and multi-voltage designs.

Supply support for 74LV164PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability, energy efficiency, and manufacturability.

The 74LV164PW,118 belongs to Nexperia's LV (Low-Voltage) logic family, engineered specifically for robust operation across 1.0 V to 5.5 V supply rails and extended industrial temperature ranges - targeting space-constrained, power-sensitive, and thermally demanding embedded applications.

FAQ

What is the minimum supply voltage for guaranteed operation of the 74LV164PW,118?

The 74LV164PW,118 is fully specified and guaranteed functional down to 1.0 V supply voltage, with static characteristics validated from VCC = 1.2 V and dynamic operation confirmed at 1.0 V using GND/VCC-referenced input levels. This enables direct use with 1.2 V and 1.8 V logic domains without level translation.

Can DSA and DSB be used simultaneously for data input?

No - DSA and DSB are logically AND-gated: only one serves as the active data path while the other acts as an enable. When DSB = HIGH, data on DSA is loaded; when DSA = HIGH, data on DSB is loaded. Simultaneous assertion of both inputs does not produce undefined behavior but results in no data shift, as both enables are inactive.

Is the exposed thermal pad on the TSSOP14 package electrically connected?

No - the exposed pad in the SOT402-1 (TSSOP14) package for 74LV164PW,118 is not electrically connected to any internal node. Nexperia documentation explicitly states it has "no electrical or mechanical requirement to solder" and should remain floating or be tied to VCC only if soldered, with no grounding or signal connection permitted.

How does the master reset (MR) interact with the clock (CP) during operation?

MR is asynchronous and dominant: asserting MR LOW immediately forces Q0–Q7 to LOW within t_PHL (≤29 ns at 3.3 V), regardless of CP state or timing. MR deassertion (HIGH) does not trigger a shift - the register remains in its last cleared state until the next valid CP rising edge loads new data from DSA or DSB.

74LV164PW,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74LV

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: Shift Register

Output Type:: Push-Pull

Number of Elements:: 1

Number of Bits per Element:: 8

Function:: Serial to Parallel

Voltage - Supply:: 1V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

74LV164PW,118 FAQ

1.How can I place an order for 74LV164PW,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LV164PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LV164PW,118 reliable?

The price and inventory of 74LV164PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV164PW,118 is usually 5 days.

3.What payment methods are accepted for 74LV164PW,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV164PW,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LV164PW,118?

74LV164PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LV164PW,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LV164PW,118?

For technical support, including 74LV164PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV164PW,118 requirements.

6.How does Aetrix verify that 74LV164PW,118 is sourced from the original manufacturer or authorized distributors?

All 74LV164PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV164PW,118 meets industry standards.

7.What is the process for return or replacement of 74LV164PW,118?

All 74LV164PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV164PW,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LV164PW,118 part is unused and in its original packaging.

Return procedure for 74LV164PW,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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