Nexperia USA Inc. 74LV1T87GVH

Overview

74LV1T87GV from Nexperia is a single-supply, level-translating 2-input EXCLUSIVE-NOR gate in SC-74A (SOT753) package, supporting bidirectional voltage translation between 1.2 V–5.0 V logic domains. It features 5 V tolerant inputs, operates from -40 °C to +125 °C, and delivers propagation delays as low as 3.4 ns at 5.0 V/15 pF - enabling use in mixed-voltage I/O interfacing for microcontroller peripherals and FPGA configuration buses.

For engineers reviewing the 74LV1T87GV datasheet, 74LV1T87GV pinout, 74LV1T87GV application, or 74LV1T87GV equivalent, this device serves as a compact, single-gate logic translator where space-constrained PCBs require deterministic EXNOR logic with rail-to-rail output referencing and robust ESD protection (HBM >2000 V, CDM >1000 V).

Technical Context

The 74LV1T87GV implements true EXNOR logic (Y = A ⊙ B) using CMOS circuitry with input thresholds dynamically scaled to VCC, enabling reliable up-translation (e.g., 1.8 V inputs → 3.3 V outputs at VCC = 3.3 V) and down-translation (e.g., 5.0 V inputs → 3.3 V outputs at VCC = 3.3 V). Its 5 V tolerant inputs eliminate external clamping diodes in legacy 5 V system interfaces.

Static performance is specified across -40 °C to +125 °C with VIH/VIL thresholds tightly tracked to VCC (e.g., VIH = 0.65 × VCC min at 3.0–3.6 V), while dynamic behavior includes CL-dependent tpd ranging from 3.4 ns (5.0 V/15 pF) to 14.2 ns (1.8 V/30 pF), and CPD from 4.1 pF (1.8 V) to 11.4 pF (5.0 V).

Key Specifications

Pinout & Package

74LV1T87GV uses the SC-74A (SOT753) surface-mount package: plastic, 5-terminal, no leads, body size 3.1 mm × 1.7 mm × 1.3 mm, with gull-wing leads and pin 1 indicator in lower-left corner below marking code "SD".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar single-gate translating logic applications.

Compared with 74LV1T87GV, the 74LVC1G86GV requires external inversion to achieve EXNOR behavior and adds timing uncertainty, while the SN74LVC1G97DBVR trades minimal functional flexibility for increased supply current and package size - making the 74LV1T87GV optimal for dedicated, low-power, space-constrained EXNOR translation.

Availability

74LV1T87GV is available at Aetrix Electronics and suitable for industrial sensor hubs, USB-C port controllers, and FPGA configuration interfaces requiring stable component supply across extended temperature ranges and mixed-voltage designs.

Supply support for 74LV1T87GV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with manufacturing rooted in process consistency and automotive-grade quality systems.

The 74LV1T series targets space- and power-constrained logic translation needs in portable, industrial, and telecom equipment - delivering single-gate functionality with minimal footprint and guaranteed level-shifting performance.

FAQ

Can 74LV1T87GV operate with VCC = 1.6 V?

Yes - the datasheet specifies VCC minimum as 1.6 V under Recommended Operating Conditions. At this voltage, VIH is guaranteed ≥0.94 V and tpd extends to 14.2 ns (1.8 V/30 pF condition applies conservatively), supporting ultra-low-power wake-up logic in battery-powered IoT nodes where 1.6 V represents end-of-life cell voltage.

Is pin 1 orientation consistent across SOT753 and SOT353-1 packages?

Yes - both SOT753 (74LV1T87GV) and SOT353-1 (74LV1T87GW) place pin 1 in the lower-left corner beneath the marking code "SD", with identical pin 1 index location relative to the package body edge and lead formation, ensuring drop-in layout compatibility during package migration.

Does the 5 V input tolerance apply during power-down (VCC = 0 V)?

No - the 5 V tolerant input rating assumes VCC ≥ 0.5 V. When VCC = 0 V, Table 5 Limiting Values restricts VI to −0.5 V to +4.6 V in power-off state; exceeding +4.6 V risks latch-up or damage, so external clamping is required for hot-plug scenarios with unpowered VCC.

How does propagation delay vary with load capacitance at VCC = 3.3 V?

At VCC = 3.3 V, tpd increases from 4.2 ns (typical) at CL = 15 pF to 8.4 ns (max) at CL = 30 pF per Table 8. This 100% increase reflects dominant RC delay contribution; design must limit total node capacitance (PCB + probe + input) to ≤20 pF to maintain <6 ns delay in timing-critical paths.