NXP Semiconductors 74LV367D,112
- Part No.:
- 74LV367D,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LV367D,112.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:3,575
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Product details
Overview
74LV367D,112 from NXP Semiconductors (formerly Philips) is a hex non-inverting 3-state buffer/line driver in SO16 package, operating from 1.0 V to 3.6 V supply, with 8 ns typical propagation delay at VCC = 3.3 V and CL = 15 pF, supporting bus driving up to 8 mA per output, used in low-voltage digital interface isolation and address/data bus control.
For engineers reviewing the 74LV367D,112 datasheet, 74LV367D,112 pinout, 74LV367D,112 application, or 74LV367D,112 equivalent, key selection considerations include 3-state enable timing (tPZH/tPLZ ≤ 30 ns), input compatibility with TTL levels at VCC ≥ 2.7 V, ground bounce (VOLP = 0.8 V) and undershoot (VOHV = 2 V) performance at 3.3 V, and MSI-level quiescent current (ICC ≤ 160 µA).
Technical Context
The 74LV367D,112 implements six independent non-inverting buffers, each with active-low 3-state enable (1OE, 2OE) controlling two outputs per group. Its CMOS structure ensures rail-to-rail output swing and low static power consumption across the full 1.0–3.6 V VCC range.
It is functionally and pin-compatible with 74HC367 and 74HCT367 but optimized for lower voltage operation and reduced switching noise - evidenced by specified VOLP (0.8 V) and VOHV (2 V) at VCC = 3.3 V, and input thresholds compliant with TTL logic when VCC ≥ 2.7 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.0 V to 3.6 V - supports single-supply operation in 1.2 V, 1.8 V, 2.5 V, and 3.3 V systems without level shifters |
| tPHL/tPLH | 8 ns typical @ VCC = 3.3 V, CL = 15 pF - enables high-speed bus buffering in sub-10 ns timing-critical paths |
| IO Sink/Source | ±35 mA per output - sufficient for direct drive of 50 Ω transmission lines or multiple CMOS inputs |
| VIH/VIL | VIH = 2.0 V min @ VCC = 2.7–3.6 V - accepts standard TTL-high inputs without translation |
| IOZ (OFF-state) | 10 µA max @ VCC = 3.6 V - ensures minimal leakage during 3-state hold in shared-bus architectures |
| ICC (Quiescent) | 160 µA max @ VCC = 3.6 V - enables low-power standby in battery-backed or always-on interfaces |
Pinout & Package
74LV367D,112 is housed in a 16-pin plastic small outline package (SO16, SOT109-1), 3.9 mm body width, with 1.27 mm pitch, surface-mount compatible, rated for –40°C to +125°C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - each controls three outputs (1Y–3Y on OE1, 4Y–6Y on OE2) |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Non-inverting data inputs - accept TTL- or CMOS-level signals across full VCC range |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Buffered non-inverting outputs - drive buses or loads with 3-state capability and ±35 mA capability |
| 8 | GND | Ground reference - common return for all I/O and supply currents |
| 16 | VCC | Positive supply - powers internal logic and output drivers; decoupling required near pin |
Key Features
| Feature | Design Value |
|---|---|
| Low-voltage operation | Functional down to VCC = 1.0 V with guaranteed DC specs from 1.2 V - enables direct integration into ultra-low-power microcontroller I/O expansion |
| TTL-input compatibility | VIH ≥ 2.0 V at VCC = 2.7–3.6 V - eliminates need for external level translators when interfacing legacy 5 V TTL peripherals |
| Controlled switching noise | VOLP = 0.8 V and VOHV = 2.0 V @ VCC = 3.3 V - reduces signal integrity risk in dense PCB layouts with shared ground planes |
| Bus-driver output strength | 8 mA sink/source capability per output at VCC = 3.0 V - supports termination-driven parallel bus designs without external drivers |
| MSI quiescent current | ICC ≤ 160 µA @ VCC = 3.6 V - minimizes system standby power in always-on industrial control modules |
Applications
| Industrial PLC Backplane Interface | Low-Power Microcontroller I/O Expander |
|---|---|
Use Scenario: Isolating and buffering address/data lines between CPU module and modular I/O cards in DIN-rail mounted PLCs. IC Role / Device Role / Timing Role: Hex 3-state buffer providing direction-controlled bus separation and noise-isolated signal routing. Use Value: Enables hot-swap-safe bus arbitration via OE control and meets EMI limits with verified VOLP/VOHV at 3.3 V operation. |
Use Scenario: Extending GPIO count of ARM Cortex-M0+ MCU in portable medical sensor hub with strict 1.8 V/3.3 V mixed-supply constraints. IC Role / Device Role / Timing Role: Non-inverting level-shifting buffer translating 1.8 V logic to 3.3 V peripheral bus while maintaining timing integrity. Use Value: Eliminates discrete level shifters; VIH compatibility and 8 ns tPD ensure no timing penalty in 20 MHz SPI/parallel interface paths. |
| Automotive Body Control Module Bus Driver | Test Equipment Digital Pattern Generator |
Use Scenario: Driving multiplexed sensor readout lines in under-hood BCM where temperature range extends to +125°C. IC Role / Device Role / Timing Role: Robust 3-state line driver enabling shared diagnostic bus access among multiple ECUs. Use Value: Guaranteed operation over –40°C to +125°C with <10 µA IOZ ensures reliable bus release during sleep mode. |
Use Scenario: Generating synchronized 6-bit parallel stimulus patterns for IC functional testing at up to 100 MHz effective rate. IC Role / Device Role / Timing Role: High-fidelity non-inverting buffer ensuring clean edge transitions and minimal skew across all six channels. Use Value: 8 ns tPD matching and <3.5 pF CI minimize pattern jitter and inter-channel skew in automated test fixtures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC367APW,118 | Lower ICC (max 10 µA), higher speed (tPD = 5.2 ns @ 3.3 V), but only rated to +85°C | Suitable for commercial-grade portable equipment; not qualified for extended temperature industrial use | Select when lowest static power and fastest timing are critical, and ambient does not exceed +85°C |
| SN74LV367ADBR | TI version with identical pinout and AC/DC specs, but different thermal derating (5.5 mW/K above +60°C for TSSOP) | Same functional behavior; differs only in packaging reliability data and qualification documentation | Choose for TI-aligned BOMs or when leveraging TI's long-term availability programs |
Compared with 74LVC367APW,118 and SN74LV367ADBR, the 74LV367D,112 offers broader temperature support (–40°C to +125°C) and proven robustness in automotive and industrial bus environments, while maintaining full pin and functional compatibility with legacy 74HC/HCT367 designs.
Availability
74LV367D,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, low-power microcontroller I/O expansion, and automated test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LV367D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors, headquartered in Eindhoven, Netherlands, is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The 74LV367D,112 belongs to NXP's legacy LV logic family, designed specifically for low-voltage, high-noise-immunity digital interface bridging in mixed-supply systems where compatibility with both CMOS and TTL signaling is required.
FAQ
What is the maximum operating temperature for the 74LV367D,112?
74LV367D,112 is fully specified for continuous operation from –40°C to +125°C ambient temperature, with DC and AC characteristics guaranteed across this full range per the Philips/NXP product specification. Derating applies above +70°C for SO16 package power dissipation (8 mW/K), consistent with JEDEC MS-012 standards.
Does the 74LV367D,112 support TTL-level inputs at 3.3 V supply?
Yes, the 74LV367D,112 accepts TTL input levels when VCC is between 2.7 V and 3.6 V: VIH is guaranteed ≥ 2.0 V and VIL ≤ 0.8 V, matching standard TTL thresholds. This allows direct connection to 5 V TTL outputs without level-shifting circuitry, as confirmed in the DC Characteristics table on page 5 of the 1998 datasheet.
What is the output drive capability of the 74LV367D,112?
The 74LV367D,112 provides ±35 mA DC output current per buffer (nY) when VO is between –0.5 V and VCC + 0.5 V, and supports bus-driver operation with 8 mA sink/source capability at VCC = 3.0 V and VOH/VOL limits defined in the DC Characteristics table - sufficient for driving 50 Ω transmission lines or fan-out to 10+ CMOS loads.
Is the 74LV367D,112 pin-compatible with the 74HC367?
Yes, the 74LV367D,112 is explicitly stated in its datasheet to be pin and function compatible with 74HC367 and 74HCT367. Pin numbering, logic function, and 3-state enable behavior match identically, allowing drop-in replacement in existing designs - though voltage range and noise performance differ due to LV-family optimization.
What is the typical propagation delay of the 74LV367D,112 at 3.3 V?
The 74LV367D,112 has a typical propagation delay (tPHL/tPLH) of 8 ns when VCC = 3.3 V, CL = 15 pF, and Tamb = 25°C, as listed in the Quick Reference Data table on page 2 of the datasheet. This value is measured from input (nA) to corresponding output (nY) under standard load conditions.
74LV367D,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LV
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
74LV367D,112 FAQ
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The price and inventory of 74LV367D,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV367D,112 is usually 5 days.
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For technical support, including 74LV367D,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV367D,112 requirements.
6.How does Aetrix verify that 74LV367D,112 is sourced from the original manufacturer or authorized distributors?
All 74LV367D,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV367D,112 meets industry standards.
7.What is the process for return or replacement of 74LV367D,112?
All 74LV367D,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV367D,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV367D,112 part is unused and in its original packaging.
Return procedure for 74LV367D,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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