NXP Semiconductors 74LV367DB,112
- Part No.:
- 74LV367DB,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74LV367DB,112.pdf
- Description:
- IC BUF NON-INVERT 3.6V 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,440
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74LV367DB,112 from NXP Semiconductors (formerly Philips) is a hex non-inverting 3-state buffer/line driver optimized for low-voltage operation from 1.0 V to 3.6 V. It features six independent channels, active-low output enables (1OE, 2OE), bus-driver output capability up to 8 mA sink/source at 3.0 V, and propagation delay of 10 ns typical at VCC = 3.3 V, CL = 15 pF - used in address/data bus interfacing and level translation between mixed-voltage logic domains.
For engineers reviewing the 74LV367DB,112 datasheet, 74LV367DB,112 pinout, 74LV367DB,112 application, or 74LV367DB,112 equivalent, key selection criteria include its 3.3 V–compatible TTL input thresholds, ground-bounce performance (VOLP = 0.8 V @ 3.3 V), VOH undershoot control (VOHV = 2 V), and SSOP-16 package suitability for high-density PCB layouts.
Technical Context
The 74LV367DB,112 implements six independent CMOS buffer stages with dual active-low 3-state enable controls (1OE for channels 1–3, 2OE for channels 4–6), enabling selective bus isolation. Its input structure accepts TTL-level signals when VCC ≥ 2.7 V, while maintaining full CMOS noise immunity and rail-to-rail output swing under load.
Designed as a low-voltage drop-in functional replacement for 74HC/HCT367, it operates across –40°C to +125°C with guaranteed DC characteristics from VCC = 1.2 V to 3.6 V and supports dynamic loading up to 50 pF per output with tr/tf ≤ 2.5 ns input edges.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.0 V to 3.6 V - supports single-supply operation in 1.2 V, 1.8 V, 2.5 V, and 3.3 V systems without level shifters. |
| Propagation Delay | 10 ns typical (nA to nY, CL = 15 pF, VCC = 3.3 V) - enables reliable timing in 50 MHz+ bus interfaces. |
| Output Drive | ±8 mA at VCC = 3.0 V - sufficient to drive standard 50 Ω transmission lines or multiple CMOS inputs (fan-out ≥ 20). |
| Input Thresholds | VIH = 2.0 V, VIL = 0.8 V @ VCC = 3.3 V - compatible with TTL outputs and robust against noise in mixed-signal environments. |
| 3-State Leakage | IOZ ≤ 10 µA @ VCC = 3.6 V - ensures minimal bus contention current during high-impedance state. |
| Power Dissipation Cap | CPD = 30 pF per buffer - allows accurate dynamic power estimation (PD = CPD × VCC² × fi) for thermal design. |
Pinout & Package
74LV367DB,112 is housed in a 16-pin plastic SSOP Type II package (SOT338-1), 5.3 mm body width, 0.65 mm lead pitch, surface-mount compatible with standard reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low enable inputs controlling 3-state output groups (pins 1→1Y–3Y; pin 15→4Y–6Y). |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Non-inverting data inputs - accept TTL/CMOS logic levels; VIH/VIL thresholds scale with VCC. |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Buffered non-inverting outputs - drive buses or downstream logic; support high-impedance OFF-state when OE = HIGH. |
| 8 | GND | Ground reference for all internal circuitry and I/O - must be low-impedance connection to minimize ground bounce. |
| 16 | VCC | Positive supply rail - decoupling capacitor (100 nF) required within 5 mm for stable 3-state switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Low-Voltage Operation | Functional down to 1.0 V supply - enables direct interface with ultra-low-power microcontrollers and battery-backed subsystems. |
| TTL-Compatible Inputs | Accepts 2.0 V VIH min at VCC = 3.3 V - eliminates need for external level translators when interfacing legacy 5 V TTL peripherals. |
| Controlled Output Transients | VOLP = 0.8 V and VOHV = 2.0 V @ 3.3 V - reduces signal integrity risk in high-speed bus switching and EMI-sensitive applications. |
| High-Density Packaging | SOT338-1 SSOP footprint - saves >40% board area vs. SOIC-16 while maintaining same pin count and routing compatibility. |
Applications
| Memory Address Bus Buffering | Industrial PLC I/O Expansion |
|---|---|
Use Scenario: Isolating and driving 16-bit address lines between a 3.3 V microcontroller and multiple SRAM/Flash devices sharing a common data/address bus. IC Role / Device Role / Timing Role: Hex non-inverting buffer with group-selectable 3-state control - enables time-multiplexed memory access without bus contention. Use Value: Propagation delay ≤10 ns ensures setup/hold timing margins are preserved across temperature extremes (–40°C to +125°C). | Use Scenario: Interfacing a 24 V digital input module to a 3.3 V FPGA-based controller via opto-isolated signal conditioning. IC Role / Device Role / Timing Role: Level-translating line driver - converts 3.3 V logic outputs to robust 8 mA bus-compatible signals for backplane distribution. Use Value: ±8 mA drive strength sustains signal integrity over 15 cm ribbon-cable runs with 50 pF load per node. |
| Automotive Body Control Module | Test Equipment Signal Routing |
Use Scenario: Managing multiplexed sensor data paths (e.g., door lock status, window position) in a CAN-connected BCM operating at 3.3 V. IC Role / Device Role / Timing Role: Selectively enabled buffer - isolates diagnostic test ports from main bus during normal operation using OE-controlled 3-state mode. Use Value: IOZ ≤ 10 µA guarantees <1 µA total leakage across six channels - critical for low-quiescent-current sleep-mode compliance. | Use Scenario: Reconfigurable signal path switching in automated test equipment where DUT I/O lines must be dynamically routed to measurement instruments. IC Role / Device Role / Timing Role: Bidirectional-capable bus driver - used in unidirectional mode to fan out trigger/control signals with precise edge control. Use Value: VOLP/VOHV specs ensure sub-1 ns jitter contribution to 100 MHz clock distribution networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC367PW,118 | Same pinout, identical function, but LVC family offers higher drive (24 mA) and tighter VCC range (1.65–3.6 V); lower ICC (10 µA max). | Better suited for high-fanout, low-noise 3.3 V systems; not rated for 1.2 V operation like LV. | Select 74LVC367PW,118 if drive strength >8 mA or quiescent current <20 µA is required; verify VCC ≥1.65 V. |
| SN74LVTH367PWR | TI part with TTL-compatible outputs (VOL ≤0.55 V @ 8 mA), same 16-pin TSSOP package; wider temp range (–40°C to +125°C) but no 1.0 V operation. | Preferred for legacy 5 V system integration where output voltage undershoot must be minimized. | Choose SN74LVTH367PWR only when interfacing with older 5 V TTL loads requiring guaranteed VOH ≥2.7 V and VOL ≤0.55 V. |
Compared with 74LV367DB,112, the 74LVC367PW,118 delivers higher drive and lower static power but sacrifices 1.0–1.65 V operation; the SN74LVTH367PWR adds TTL-output compatibility at the cost of reduced low-voltage flexibility - making 74LV367DB,112 optimal for wide-input-voltage, space-constrained industrial designs.
Availability
74LV367DB,112 is available at Aetrix Electronics and suitable for industrial automation controllers, automotive body electronics, test instrumentation, and high-reliability embedded systems requiring stable component supply across extended temperature ranges.
Supply support for 74LV367DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with roots in Philips' pioneering logic IC development.
The 74LV367DB,112 belongs to NXP's legacy LV (Low-Voltage) logic family, engineered for interoperability across mixed-voltage digital systems while maintaining backward compatibility with HC/HCT timing and pinouts.
FAQ
What is the minimum supply voltage at which 74LV367DB,112 guarantees functionality?
The 74LV367DB,112 is fully functional down to VCC = 1.0 V, with input logic levels referenced to GND or VCC. However, DC electrical characteristics (VIH, VIL, VOH, VOL) are guaranteed only from VCC = 1.2 V to 3.6 V per the datasheet's recommended operating conditions. Below 1.2 V, operation is functional but not characterized.
Does 74LV367DB,112 support true bidirectional data flow?
No, the 74LV367DB,112 is a unidirectional non-inverting buffer with fixed input (A) and output (Y) terminals. It does not contain internal direction control or bus transceiver logic. For bidirectional applications, discrete direction-control logic or dedicated transceivers like 74LVX245 must be used alongside 74LV367DB,112.
Can 74LV367DB,112 replace 74HC367 in an existing design?
Yes - the 74LV367DB,112 is pin and function compatible with 74HC367 and 74HCT367. Key differences include lower VCC range (1.0–3.6 V vs. 2.0–6.0 V), improved noise immunity at 3.3 V, and reduced ground bounce. No PCB changes are needed, but verify that VCC and input signal levels fall within LV specifications.
What is the maximum capacitive load each output of 74LV367DB,112 can drive reliably?
Each output of the 74LV367DB,112 is characterized up to CL = 50 pF in AC specifications (propagation delay, enable/disable times). Driving loads beyond 50 pF increases delay and may degrade edge rates; for >50 pF, use series termination or buffer staging. The 8 mA drive rating assumes resistive loading, not pure capacitance.
Is 74LV367DB,112 qualified for automotive applications?
The 74LV367DB,112 is specified for operation from –40°C to +125°C and meets JEDEC standards for industrial-grade reliability. While not AEC-Q100 qualified, its extended temperature range and robustness make it widely deployed in non-safety-critical automotive modules such as body control units and infotainment interfaces - subject to customer qualification.
74LV367DB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LV
- Package/Case:
- 16-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
74LV367DB,112 FAQ
1.How can I place an order for 74LV367DB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LV367DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LV367DB,112 reliable?
The price and inventory of 74LV367DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV367DB,112 is usually 5 days.
3.What payment methods are accepted for 74LV367DB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV367DB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LV367DB,112?
74LV367DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LV367DB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LV367DB,112?
For technical support, including 74LV367DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV367DB,112 requirements.
6.How does Aetrix verify that 74LV367DB,112 is sourced from the original manufacturer or authorized distributors?
All 74LV367DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV367DB,112 meets industry standards.
7.What is the process for return or replacement of 74LV367DB,112?
All 74LV367DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV367DB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV367DB,112 part is unused and in its original packaging.
Return procedure for 74LV367DB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LV367DB,112 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

