My Inquiry
My Account
NXP Semiconductors 74LV367N,112
- Part No.:
- 74LV367N,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
74LV367N,112.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 16DIP
- Quantity:
- Payment:
- Shipping:
Inventory:3,009
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74LV367N,112 from NXP Semiconductors (formerly Philips) is a hex non-inverting 3-state buffer/line driver in a 16-pin plastic DIL package. It operates from 1.0 V to 3.6 V, delivers ±35 mA bus-driver output current, and achieves 10 ns typical propagation delay at VCC = 3.3 V with CL = 15 pF - used for bidirectional bus interfacing in low-voltage industrial control backplanes.
For engineers reviewing the 74LV367N,112 datasheet, 74LV367N,112 pinout, 74LV367N,112 application, or 74LV367N,112 equivalent, key selection criteria include its 3-state enable timing (tPZH/tPLZ ≤ 30 ns), TTL-input compatibility at VCC ≥ 2.7 V, ground-bounce performance (VOLP = 0.8 V), and operation across –40°C to +125°C ambient.
Technical Context
The 74LV367N,112 implements six independent non-inverting buffers, each with active-low 3-state enable (1OE, 2OE) controlling three outputs per group. Its CMOS input structure accepts TTL-level signals when VCC is 2.7–3.6 V, while maintaining full logic threshold compliance down to 1.2 V supply.
Propagation delay is load- and voltage-dependent: 19 ns max at VCC = 3.0–3.6 V and CL = 50 pF; 3-State enable/disable times are specified separately (tPZH ≤ 30 ns, tPHZ ≤ 36 ns at VCC = 3.3 V). Output drive strength supports direct connection to 50-pF transmission lines without external termination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.0 V to 3.6 V - enables interoperability with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains |
| Propagation Delay (tPHL/tPLH) | 10 ns typical @ VCC = 3.3 V, CL = 15 pF - ensures sub-100 MHz bus timing margin |
| Output Drive (IO) | ±35 mA per buffer - sufficient to drive standard 50 Ω PCB traces or multiple CMOS inputs |
| Input Thresholds (VIH/VIL) | VIH = 2.0 V, VIL = 0.8 V @ VCC = 3.3 V - guarantees reliable TTL-level signal recognition |
| 3-State Enable Time (tPZH) | 30 ns max @ VCC = 3.3 V - limits bus contention window during direction switching |
| Quiescent ICC | 20 µA typical @ VCC = 3.6 V - supports low-power standby in battery-backed systems |
| Operating Temperature | –40°C to +125°C - qualified for under-hood automotive and industrial motor-control environments |
Pinout & Package
74LV367N,112 uses a 16-pin plastic dual in-line package (DIP16, SOT38-4) with 300-mil width and through-hole mounting. Pin pitch is 2.54 mm; body height is 3.3 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - assert LOW to activate corresponding group of three outputs |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Non-inverting data inputs - accept TTL/CMOS logic levels; VIH/VIL defined per VCC |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Buffered non-inverting outputs - high-drive capability (±35 mA), 3-state capable |
| 8 | GND | Logic and power ground reference - must be low-impedance connection to minimize ground bounce |
| 16 | VCC | Positive supply rail - bypass with 100 nF ceramic capacitor near pin for noise suppression |
Key Features
| Feature | Design Value |
|---|---|
| Low-voltage operation | Functional down to 1.0 V supply - supports ultra-low-power sensor interface subsystems |
| TTL-input compatibility | Valid at VCC = 2.7–3.6 V - eliminates level-shifter need when interfacing legacy 5 V peripherals |
| Controlled output transition | VOLP = 0.8 V, VOHV = 2.0 V @ VCC = 3.3 V - reduces EMI and crosstalk in dense routing |
| High-temperature rating | Specified up to +125°C ambient - suitable for engine-control modules and power-conversion controllers |
| Bus-driver output stage | ±35 mA sink/source per output - drives 50 pF loads directly without external buffers |
Applications
| Industrial PLC Backplane Interface | Automotive Body Control Module |
|---|---|
Use Scenario: Isolating and buffering address/data lines between microcontroller and I/O expansion ASIC on a 24 V-powered PLC rack. IC Role / Device Role / Timing Role: Hex non-inverting buffer with 3-state control enables time-multiplexed bus sharing between CPU and peripheral cards. Use Value: 10 ns propagation delay and 30 ns enable time ensure deterministic cycle timing; ±35 mA drive sustains signal integrity over 15 cm backplane traces. |
Use Scenario: Level translation and bus isolation between 3.3 V CAN controller and 5 V lamp-driver ASIC in vehicle lighting ECU. IC Role / Device Role / Timing Role: 3-state buffer provides directional control for shared diagnostic bus while tolerating 12 V system transients via robust input clamping. Use Value: TTL-input compatibility at VCC = 3.3 V allows direct connection to CAN controller outputs; –40°C to +125°C rating matches under-hood thermal requirements. |
| Low-Power Sensor Hub Interface | Legacy Equipment Retrofit Adapter |
Use Scenario: Aggregating digital outputs from six MEMS pressure sensors (1.8 V logic) into a single 3.3 V SPI-compatible data bus. IC Role / Device Role / Timing Role: Voltage-translating buffer with 3-state outputs prevents bus contention during multi-sensor polling sequences. Use Value: 1.0 V minimum VCC enables direct use with 1.2 V LDO rails; 20 µA quiescent ICC minimizes idle power in always-on monitoring nodes. |
Use Scenario: Replacing obsolete 74LS367 in aging test equipment requiring 3.3 V compatibility and reduced heat dissipation. IC Role / Device Role / Timing Role: Pin- and function-compatible upgrade delivering identical logic behavior with lower supply voltage and improved noise immunity. Use Value: Identical pinout and truth table allow drop-in replacement; 3.3 V operation cuts power by >70% versus LS family at same frequency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex non-inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC367PW,118 | Same logic function, TSSOP16 package (4.4 mm width); 3.6 V absolute max VCC vs. 4.6 V for LV series | Higher density layout; not rated for +125°C operation (max +85°C) | Select when board space is constrained and extended temperature is not required |
| SN74LV367ADBR | TI variant: identical electrical specs but different AC test conditions (CL = 50 pF vs. 15 pF); same DIL footprint unavailable | SOIC-16 only; requires PCB redesign; slightly higher ICC (30 µA typical) | Select when sourcing from TI-authorized channels and SOIC packaging is acceptable |
Compared with 74LVC367PW,118 and SN74LV367ADBR, the 74LV367N,112 uniquely combines through-hole DIP16 mechanical compatibility, full –40°C to +125°C qualification, and 4.6 V absolute maximum VCC tolerance - critical for industrial retrofit and high-reliability thermal environments.
Availability
74LV367N,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, and low-power sensor hub interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LV367N,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors, headquartered in Eindhoven, Netherlands, designs high-performance analog, logic, and interface ICs for automotive, industrial, and communication markets.
The 74LV367N,112 belongs to NXP's legacy LV logic family, engineered specifically for robust low-voltage operation (1.0–3.6 V) with TTL-input compatibility and extended temperature resilience in mission-critical control systems.
FAQ
What is the absolute maximum supply voltage for the 74LV367N,112?
The 74LV367N,112 has an absolute maximum DC supply voltage (VCC) rating of –0.5 V to +4.6 V referenced to GND. Operation beyond 3.6 V is not recommended for functional reliability, but transient excursions up to +4.6 V will not cause immediate damage if duration and current limits are observed per the Absolute Maximum Ratings table.
Does the 74LV367N,112 support TTL-level inputs at 3.3 V supply?
Yes, the 74LV367N,112 explicitly supports TTL input thresholds when VCC is between 2.7 V and 3.6 V. At VCC = 3.3 V, VIH is guaranteed ≥ 2.0 V and VIL ≤ 0.8 V - fully compatible with standard 5 V TTL output swing levels without external level shifting.
What is the maximum output current per pin on the 74LV367N,112?
The 74LV367N,112 delivers ±35 mA DC output current per buffer (nY pin) under bus-driver conditions. This rating applies when VO is within –0.5 V to VCC + 0.5 V and is validated across the full operating temperature range of –40°C to +125°C.
Is the 74LV367N,112 pin-compatible with the 74HC367?
Yes, the 74LV367N,112 is pin and function compatible with the 74HC367 and 74HCT367. All share identical pin numbering, logic function, and truth table. However, the 74LV367N,112 operates at lower supply voltages (1.0–3.6 V) and exhibits faster propagation delays and lower power consumption than HC/HCT variants at equivalent VCC.
What package type does the 74LV367N,112 use?
The 74LV367N,112 uses a 16-pin plastic dual in-line package (DIP16) conforming to SOT38-4 mechanical dimensions: 300-mil width, 2.54 mm pin pitch, and through-hole mounting. It is distinct from SO16 (SOT109-1), SSOP16 (SOT338-1), and TSSOP16 (SOT403-1) variants of the same logic function.
74LV367N,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LV
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-DIP
74LV367N,112 FAQ
1.How can I place an order for 74LV367N,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LV367N,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LV367N,112 reliable?
The price and inventory of 74LV367N,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV367N,112 is usually 5 days.
3.What payment methods are accepted for 74LV367N,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV367N,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LV367N,112?
74LV367N,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LV367N,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LV367N,112?
For technical support, including 74LV367N,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV367N,112 requirements.
6.How does Aetrix verify that 74LV367N,112 is sourced from the original manufacturer or authorized distributors?
All 74LV367N,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV367N,112 meets industry standards.
7.What is the process for return or replacement of 74LV367N,112?
All 74LV367N,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV367N,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV367N,112 part is unused and in its original packaging.
Return procedure for 74LV367N,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LV367N,112 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments
-
SN74LVC2G17DBVR
Texas Instruments
-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments
-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
