NXP Semiconductors 74LV4052PW/AUJ
- Part No.:
- 74LV4052PW/AUJ
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74LV4052PW/AUJ.pdf
- Description:
- IC SWITCH SP4T X 2 85OHM 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LV4052PW/AUJ from Nexperia is a dual 4-channel analog multiplexer/demultiplexer in TSSOP16 package, operating from 1.0 V to 6.0 V supply. It features two independent 1-of-4 bidirectional switches (1Z/1Y0–1Y3 and 2Z/2Y0–2Y3), common digital control (E, S0, S1), and rail-to-rail analog signal handling with ≤60 Ω typical ON resistance at 4.5 V. It enables flexible signal routing in low-voltage mixed-signal instrumentation.
For engineers reviewing the 74LV4052PW/AUJ datasheet, 74LV4052PW/AUJ pinout, 74LV4052PW/AUJ application, or 74LV4052PW/AUJ equivalent, key selection criteria include guaranteed operation down to 1.0 V, ±3 V analog signal compatibility via logic-level translation, break-before-make switching behavior, -40 °C to +125 °C temperature range, and TSSOP16 footprint suitability for space-constrained PCB layouts.
Technical Context
The 74LV4052PW/AUJ implements two independent CMOS analog switches controlled by a shared 2-bit binary decoder (S0/S1) and active-low enable (E). Each switch supports bidirectional analog signal flow between four Y terminals and one Z terminal, with clamp diodes on digital inputs enabling safe interfacing to voltages exceeding VCC when current-limiting resistors are used.
Its architecture supports logic-level translation - e.g., 3 V digital control can reliably switch ±3 V analog signals - and includes built-in break-before-make timing to prevent momentary shorting during channel transitions. Static and dynamic performance is specified across -40 °C to +125 °C, with ON resistance varying predictably with VCC (e.g., 60 Ω typ. at 4.5 V, 90 Ω typ. at 3.0 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 1.0 V to 6.0 V - enables direct integration into ultra-low-voltage (1.2 V) digital systems and legacy 5 V analog subsystems without level shifters. |
| ON resistance (typ.) | 60 Ω at VCC = 4.5 V - ensures minimal signal attenuation and distortion for audio, sensor, and precision ADC/DAC interface applications. |
| Propagation delay | 3 ns to 7 ns at VCC = 6.0 V - supports high-speed signal routing in data acquisition and real-time control loops. |
| Operating temperature | -40 °C to +125 °C - qualified for industrial automation, automotive under-hood monitoring, and harsh-environment embedded systems. |
| ESD protection | HBM >2000 V, CDM >1000 V - reduces risk of field failure during handling and board assembly in high-static environments. |
| Switch capacitance | 12 pF on common pins (nZ) - limits capacitive loading and crosstalk in multi-channel analog front-ends. |
| Isolation (OFF-state) | -50 dB at 1 MHz - maintains signal integrity between inactive channels in multiplexed sensor arrays or test equipment. |
Pinout & Package
TSSOP16 package (SOT403-1), 4.4 mm body width, 0.65 mm pitch, 16-pin surface-mount outline optimized for automated assembly and thermal performance in dense layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 5, 2, 4 (2Y0–2Y3) | Independent analog I/O | Four bidirectional analog terminals for second switch; compatible with ±3 V signals when VEE = -3 V. |
| 3, 13 (2Z, 1Z) | Common analog I/O | Shared connection point per switch; supports multiplexing or demultiplexing functions with low RON path. |
| 6 (E) | Enable input (active LOW) | Global disable control; HIGH forces both switches OFF, isolating all analog paths simultaneously. |
| 9, 10 (S1, S0) | Digital select inputs | 2-bit binary address selects one of four Y channels per switch; TTL-compatible at VCC ≥ 2.7 V. |
| 7 (VEE) | Negative supply | Supports dual-supply operation (e.g., VCC = +3 V, VEE = -3 V) for true bipolar analog signal handling. |
| 8 (GND) | Ground reference | 0 V reference for digital logic and analog return path; must be low-impedance for noise-sensitive applications. |
| 11, 12, 14, 15 (1Y0–1Y3) | Independent analog I/O | Four bidirectional analog terminals for first switch; electrically identical to 2Yn pins. |
| 16 (VCC) | Positive supply | Primary power rail; supplies both digital control logic and analog switch bias; accepts 1.0–6.0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Logic-level translation | Enables 3 V digital controllers to safely route ±3 V analog signals without external level shifters or clamping circuits. |
| Break-before-make switching | Prevents momentary short-circuits between Y channels during state transitions, critical for fault-tolerant sensor multiplexing. |
| Wide supply range (1.0–6.0 V) | Eliminates need for separate voltage regulators in battery-powered IoT nodes or multi-rail industrial PLC modules. |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level B - ensures robustness against transient overcurrent events in noisy environments. |
| Low ON-resistance mismatch | ΔRON ≤ 2 Ω peak - guarantees matched gain/attenuation across channels in precision instrumentation amplifier front-ends. |
Applications
| Industrial Sensor Multiplexing | Automotive Cabin Monitoring |
|---|---|
Use Scenario: A programmable logic controller routes 8 thermocouple or RTD inputs to a single 24-bit ADC using two 74LV4052PW/AUJ devices. IC Role / Device Role / Timing Role: Dual 4:1 analog MUX provides channel-selectable signal path with <7 ns propagation delay and <60 Ω RON to preserve measurement accuracy. Use Value: Enables cost-effective expansion of analog input count without adding ADCs or degrading SNR due to low switch resistance and capacitance. | Use Scenario: In-vehicle cabin air quality system samples CO₂, humidity, and VOC sensors sequentially via shared analog front-end. IC Role / Device Role / Timing Role: Bidirectional analog switch handles ±2.5 V sensor outputs while surviving automotive temperature cycling (-40 °C to +125 °C). Use Value: Single-chip solution replaces discrete relays or larger mux ICs, reducing BOM count and PCB area in compact HVAC control modules. |
| Portable Medical Instrumentation | Test & Measurement Equipment |
Use Scenario: Handheld ECG device selects among 6 electrode inputs using cascaded 74LV4052PW/AUJ switches before amplification and digitization. IC Role / Device Role / Timing Role: Low 1.0 V minimum supply allows direct use with Li-ion battery (2.7–4.2 V), minimizing power conversion losses. Use Value: Extends battery life while maintaining clinical-grade signal fidelity via <0.4 % THD at 3 V and -50 dB isolation between inactive leads. | Use Scenario: Benchtop multimeter uses 74LV4052PW/AUJ to route DMM core between voltage, current, resistance, and capacitance measurement paths. IC Role / Device Role / Timing Role: Dual-switch architecture isolates high-impedance voltage sense lines from low-impedance current shunt paths during auto-ranging. Use Value: Prevents cross-talk-induced measurement errors and eliminates mechanical relay wear, improving long-term calibration stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC4052PW | Wider supply range (1.65–5.5 V); higher ICC (max 40 μA vs. 80 μA); identical pinout and function. | Optimized for 1.8 V/3.3 V systems only; not rated below 1.65 V - unsuitable for 1.2 V battery operation. | Select 74LVC4052PW only if design operates strictly within 1.65–5.5 V and requires lower static current. |
| ADG708BRUZ | Single 8:1 mux (vs. dual 4:1); SPI interface (vs. parallel logic); higher RON (3.5 Ω typ. at 3 V); different package (TSSOP16 same footprint but non-pin-compatible). | Requires microcontroller firmware control; better for reconfigurable channel mapping but adds software overhead. | Choose ADG708BRUZ only when dynamic channel remapping via SPI is required and layout allows redesign. |
Compared with 74LVC4052PW and ADG708BRUZ, the 74LV4052PW/AUJ uniquely supports 1.0 V operation and dual independent 4-channel routing in a fixed-logic TSSOP16 package - making it optimal for low-power, pin-constrained, and deterministic analog signal switching where firmware intervention is undesirable.
Availability
74LV4052PW/AUJ is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive cabin monitoring systems, and portable medical instrumentation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LV4052PW/AUJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable components for automotive, industrial, mobile, and computing markets.
The 74LV4052PW/AUJ belongs to Nexperia's LV logic family, engineered for ultra-low-voltage operation and robust analog switching in mixed-signal systems where power efficiency and signal integrity are critical.
FAQ
What is the minimum supply voltage supported by the 74LV4052PW/AUJ?
The 74LV4052PW/AUJ is fully specified down to 1.0 V supply voltage, with functional operation guaranteed from VCC = 1.0 V to 6.0 V. At 1.2 V, analog switch linearity degrades, so digital signal routing is recommended below that threshold. The 74LV4052PW/AUJ datasheet confirms static characteristics are guaranteed from 1.2 V, but functionality extends to 1.0 V with GND/VCC input levels.
Does the 74LV4052PW/AUJ support dual-supply operation?
Yes, the 74LV4052PW/AUJ supports dual-supply operation with VCC as positive rail and VEE as negative rail (e.g., VCC = +3.0 V, VEE = -3.0 V), enabling true bipolar analog signal handling up to ±3 V. This capability is explicitly defined in the pin description and functional diagram, and the 74LV4052PW/AUJ datasheet specifies switch voltage range from 0 V to VCC with VEE referenced separately.
What is the typical ON resistance of the 74LV4052PW/AUJ at 3.3 V supply?
At VCC = 3.3 V and ISW = 1000 μA, the 74LV4052PW/AUJ exhibits 80 Ω typical ON resistance (RON(peak)) and 60 Ω typical ON resistance (RON(rail)) when VI = GND. These values are measured across the full -40 °C to +125 °C range and appear in Table 7 of the official 74LV4052PW/AUJ datasheet.
Is the 74LV4052PW/AUJ pin-compatible with the SO16 version 74LV4052D?
No, the 74LV4052PW/AUJ (TSSOP16, SOT403-1) is not pin-compatible with the 74LV4052D (SO16, SOT109-1) despite identical pin functions - their physical footprints differ significantly (4.4 mm vs. 3.9 mm body width, different lead pitch and thermal pad configuration). The 74LV4052PW/AUJ requires a dedicated TSSOP16 land pattern and cannot be substituted without PCB revision.
What does 'break-before-make' mean for the 74LV4052PW/AUJ, and how is it implemented?
'Break-before-make' means the 74LV4052PW/AUJ disconnects the previously selected channel before connecting the newly selected one, preventing momentary short-circuits between Y terminals. This behavior is inherent to its CMOS analog switch architecture and timing design - confirmed in Section 2 of the 74LV4052PW/AUJ datasheet - and eliminates need for external timing control logic in safety-critical multiplexing.
74LV4052PW/AUJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Circuit:
- SP4T
- Multiplexer/Demultiplexer Circuit:
- 4:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 85Ohm
- Channel-to-Channel Matching (ΔRon):
- 2Ohm
- Voltage - Supply, Single (V+):
- 1V ~ 6V
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- 46ns, 32ns
- -3db Bandwidth:
- 200MHz
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 3.5pF
- Current - Leakage (IS(off)) (Max):
- 2µA
- Crosstalk:
- -60dB @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
74LV4052PW/AUJ FAQ
1.How can I place an order for 74LV4052PW/AUJ through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LV4052PW/AUJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LV4052PW/AUJ reliable?
The price and inventory of 74LV4052PW/AUJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV4052PW/AUJ is usually 5 days.
3.What payment methods are accepted for 74LV4052PW/AUJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV4052PW/AUJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LV4052PW/AUJ?
74LV4052PW/AUJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LV4052PW/AUJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LV4052PW/AUJ?
For technical support, including 74LV4052PW/AUJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV4052PW/AUJ requirements.
6.How does Aetrix verify that 74LV4052PW/AUJ is sourced from the original manufacturer or authorized distributors?
All 74LV4052PW/AUJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV4052PW/AUJ meets industry standards.
7.What is the process for return or replacement of 74LV4052PW/AUJ?
All 74LV4052PW/AUJ units undergo pre-shipment inspection (PSI). If there is an issue with 74LV4052PW/AUJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LV4052PW/AUJ part is unused and in its original packaging.
Return procedure for 74LV4052PW/AUJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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