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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Nexperia USA Inc. 74LV74D,118

Name: 74LV74D,118
Brand: Nexperia USA Inc.
SKU: 74LV74D,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74LV74D,118

Manufacturer:: Nexperia USA Inc.

Category:: Flip Flops

Package:: 14-SOIC (0.154", 3.90mm Width)

Datasheet:: 74LV74D,118.pdf

Description:: IC FF D-TYPE DUAL 1BIT 14SO

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74LV74D,118 from Nexperia is a dual positive-edge-triggered D-type flip-flop with independent asynchronous set (nSD) and reset (nRD) inputs, complementary Q/nQ outputs per channel, 1.0 V to 5.5 V supply range, and operation up to +125 °C - used in digital control logic, clock domain synchronization, and state machine sequencing in industrial PLCs and sensor interface modules.

For engineers reviewing the 74LV74D,118 datasheet, 74LV74D,118 pinout, 74LV74D,118 application, or 74LV74D,118 equivalent, key selection factors include its dual-channel edge-triggered storage behavior, 13 ns typical propagation delay at 3.3 V, ±25 mA output drive capability, and SO14 package compatibility with legacy 74-series board layouts.

Technical Context

The 74LV74D,118 implements two independent CMOS D-type flip-flops sharing no internal coupling - each with dedicated data (nD), clock (nCP), active-low set (nSD), and active-low reset (nRD) terminals. Its positive-edge triggering requires precise setup/hold timing (e.g., 8 ns setup, –2 ns hold at 3.3 V) for reliable state capture on LOW-to-HIGH transitions.

It supports wide-voltage interfacing: direct TTL-level compatibility (2.7 V–3.6 V), input clamping diodes enabling overvoltage-tolerant design with current-limiting resistors, and guaranteed operation down to 1.0 V supply - making it suitable for mixed-voltage systems and low-power battery-operated controllers.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	1.0 V to 5.5 V - enables direct integration into 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters
Propagation Delay (t_pd)	13 ns typical at V_CC = 3.3 V, C_L = 15 pF - determines maximum synchronous logic speed in state-holding paths
Maximum Clock Frequency	100 MHz typical at V_CC = 3.3 V - sets upper bound for reliable edge-triggered sampling in timing-critical control loops
Output Drive Capability	±25 mA per output - sufficient to directly drive multiple 74-series inputs or small LED indicators without buffers
Operating Temperature	–40 °C to +125 °C - qualified for under-hood automotive modules, industrial motor drives, and outdoor telecom equipment
Input Clamp Diodes	Integrated - allows safe interface to signals exceeding V_CC when used with external current-limiting resistors
ESD Protection	HBM > 2000 V, CDM > 1000 V - enhances robustness during PCB handling and system-level ESD events

Pinout & Package

74LV74D,118 uses the SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, and standard JEDEC MS-012 footprint compatible with automated assembly.

Pin/Terminal	Circuit Role	Design Meaning
1, 13	nRD (asynchronous reset)	Active-LOW direct reset for Flip-Flop 1 and 2 - forces nQ = H, nQ = L regardless of clock or data
2, 12	nD (data input)	Primary data source sampled on rising clock edge - defines next-state value for corresponding flip-flop
3, 11	nCP (clock input)	Positive-edge-triggered clock - initiates state update only on LOW-to-HIGH transition meeting setup/hold requirements
4, 10	nSD (asynchronous set)	Active-LOW direct set - forces nQ = L, nQ = H independently of clock or data
5, 9	nQ (true output)	Complementary logic state of stored data - drives downstream logic or feedback paths
6, 8	nQ (complement output)	Inverted output - eliminates need for external inverters in toggle or differential signaling applications
7	GND	Reference ground plane - must be low-impedance connection to minimize switching noise coupling
14	V_CC	Primary power supply - decoupling capacitor (100 nF) required within 5 mm of pin for stable high-speed operation

Key Features

Feature	Design Value
Wide Supply Range	1.0 V to 5.5 V operation - supports single-supply designs across legacy and ultra-low-power systems without voltage translation
Asynchronous Control	Dedicated active-LOW nSD/nRD per flip-flop - enables immediate state initialization or fault recovery independent of clock timing
CMOS Power Efficiency	ICC ≤ 20 μA typical at V_CC = 5.5 V - reduces quiescent power in always-on monitoring circuits
TTL Interface Compatibility	Direct connection to 2.7 V–3.6 V TTL outputs - eliminates level-shifter components in mixed-logic upgrades
High-Temperature Operation	Guaranteed functionality at +125 °C ambient - suitable for engine-control units and power-conversion gate drivers

Applications

Industrial Motor Control

Serial Data Synchronization

Use Scenario: Capturing encoder quadrature signals in real time to determine direction and position of AC induction motors.

IC Role / Device Role / Timing Role: Dual flip-flop acts as synchronized edge detector - one channel latches A-phase, the other latches B-phase on shared clock to resolve phase relationship.

Use Value: 13 ns propagation delay ensures sub-microsecond timing alignment between channels, preventing metastability-induced position errors at 100 kHz encoder rates.

Use Scenario: Aligning asynchronous UART receive data streams to a local system clock for glitch-free FIFO loading.

IC Role / Device Role / Timing Role: First-stage synchronizer - samples incoming RX line with local clock to eliminate setup/hold violations before feeding into shift register.

Use Value: Asynchronous nSD/nRD allow forced reset on framing errors, while 1.0 V–5.5 V supply range permits direct use with 1.8 V transceivers or 5 V microcontrollers.

Programmable Logic Sequencing

Power Supply State Management

Use Scenario: Implementing finite-state machines in FPGA-adjacent glue logic for configuration handshaking and boot sequence coordination.

IC Role / Device Role / Timing Role: Storage element in Moore-style state register - Q outputs feed combinational logic that determines next state and control signals.

Use Value: Complementary Q/nQ outputs reduce external inversion count; 100 MHz max clock supports 10 ns state transitions in high-throughput sequencers.

Use Scenario: Monitoring undervoltage lockout (UVLO) and overtemperature flags to assert controlled shutdown of DC-DC converters.

IC Role / Device Role / Timing Role: Set-reset latch holding fault condition - nSD triggers on UVLO event, nRD clears after thermal recovery and manual reset pulse.

Use Value: Direct 125 °C rating matches converter thermal profiles; clamp diodes tolerate transient overshoot on sense lines without external protection.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC74APW	Higher I_OH/I_OL (±24 mA vs ±25 mA), identical SO14 pinout, but rated only to +85 °C	Not suitable for extended-temperature industrial environments requiring +125 °C operation	Select when cost sensitivity outweighs temperature requirement and 85 °C ambient suffices
74AUP1G74GM	Single-channel, XSON-8 package, lower ICC (0.9 μA), but lacks second flip-flop and asynchronous controls	Requires two devices and external logic to replicate dual-channel asynchronous behavior	Choose only for space-constrained, ultra-low-power single-bit storage where dual functionality is not needed

Compared with SN74LVC74APW and 74AUP1G74GM, the 74LV74D,118 uniquely delivers dual independent flip-flops with full asynchronous control, 125 °C rating, and SO14 compatibility - making it the only drop-in solution for legacy 74-series designs needing extended temperature resilience and functional completeness.

Availability

74LV74D,118 is available at Aetrix Electronics and suitable for industrial motor control, serial data synchronization, programmable logic sequencing, and power supply state management requiring stable component supply across long-lifecycle production programs.

Supply support for 74LV74D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies - delivering high-performance, reliable, and scalable logic, analog, and discrete components for automotive, industrial, and consumer markets.

The 74LV74D,118 belongs to Nexperia's LV (Low-Voltage) logic family, engineered for interoperability across 1.0 V–5.5 V supply domains and designed specifically for robust, low-power digital control in harsh-environment applications.

FAQ

What is the minimum supply voltage at which 74LV74D,118 guarantees correct logic operation?

The 74LV74D,118 guarantees functional operation down to V_CC = 1.0 V, with DC electrical characteristics fully specified from 1.2 V to 5.5 V. At 1.0 V, input thresholds scale proportionally (VIH ≈ 0.9 V, VIL ≈ 0.3 V), and propagation delay increases to 70 ns - confirmed in Table 7 for –40 °C to +85 °C conditions.

Can 74LV74D,118 safely interface with 5 V TTL outputs without level shifting?

Yes - the 74LV74D,118 features integrated input clamp diodes and is explicitly rated for direct interface with TTL levels (2.7 V to 3.6 V). When interfacing with 5 V TTL, external current-limiting resistors (≥1 kΩ) must be used to limit IIK to ≤20 mA, as specified in Table 4's limiting values.

How does the asynchronous reset (nRD) behave relative to the clock edge?

nRD is asynchronous and active-LOW: asserting nRD forces nQ = H and nQ = L immediately, overriding any ongoing clock or data activity. The reset takes effect within t_rec = 6 ns (typical at 5 V), and the device remains in reset until nRD returns HIGH - no clock edge is required for entry or exit.

Is the SO14 package of 74LV74D,118 compatible with standard 74HC74 footprints?

Yes - the 74LV74D,118 in SOT108-1 (SO14) uses the same 14-pin, 1.27 mm pitch, 3.9 mm body width footprint as industry-standard 74HC74 SO14 packages. Pin numbering and function mapping (e.g., pin 1 = 1RD, pin 2 = 1D, pin 3 = 1CP) are identical, enabling direct replacement in existing layouts.

74LV74D,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74LV

Package/Case:: 14-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Set(Preset) and Reset

Type:: D-Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 110 MHz

Max Propagation Delay @ V, Max CL:: 17ns @ 5V, 50pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 12mA, 12mA

Voltage - Supply:: 1V ~ 5.5V

Current - Quiescent (Iq):: 20 µA

Input Capacitance:: 3.5 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-SO

74LV74D,118 FAQ

1.How can I place an order for 74LV74D,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LV74D,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LV74D,118 reliable?

The price and inventory of 74LV74D,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV74D,118 is usually 5 days.

3.What payment methods are accepted for 74LV74D,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV74D,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LV74D,118?

74LV74D,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LV74D,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LV74D,118?

For technical support, including 74LV74D,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV74D,118 requirements.

6.How does Aetrix verify that 74LV74D,118 is sourced from the original manufacturer or authorized distributors?

All 74LV74D,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV74D,118 meets industry standards.

7.What is the process for return or replacement of 74LV74D,118?

All 74LV74D,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV74D,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LV74D,118 part is unused and in its original packaging.

Return procedure for 74LV74D,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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