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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Nexperia USA Inc. 74LV74PW,112

Name: 74LV74PW,112
Brand: Nexperia USA Inc.
SKU: 74LV74PW,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74LV74PW,112

Manufacturer:: Nexperia USA Inc.

Category:: Flip Flops

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: 74LV74PW,112.pdf

Description:: IC FF D-TYPE DUAL 1BIT 14TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74LV74PW,112 from Nexperia is a dual positive-edge-triggered D-type flip-flop with independent asynchronous set (nSD) and reset (nRD) inputs, complementary Q/nQ outputs per channel, 1.0 V to 5.5 V supply range, -40 °C to +125 °C operation, and TSSOP14 package. It functions as a synchronous storage element in digital control logic, clock-domain synchronization, and state-holding circuits in industrial microcontroller peripherals.

For engineers reviewing the 74LV74PW,112 datasheet, 74LV74PW,112 pinout, 74LV74PW,112 application, or 74LV74PW,112 equivalent, key selection criteria include its dual-channel edge-triggered behavior, wide voltage compatibility (1.0–5.5 V), guaranteed operation at 125 °C ambient, and direct TTL-level interfacing capability at 2.7–3.6 V.

Technical Context

The 74LV74PW,112 implements two independent CMOS D-type flip-flops, each with asynchronous active-low set and reset, positive-edge clock triggering, and non-inverting/inverting outputs. Its logic conforms to IEC 60617 and IEEE Std 91-1984 standards, supporting both synchronous data capture and asynchronous state initialization.

It features input clamp diodes enabling safe interface to voltages exceeding VCC when used with current-limiting resistors, and meets JESD 78 Class II Level B latch-up immunity (>100 mA). The device operates across two temperature grades: -40 °C to +85 °C and -40 °C to +125 °C - the latter confirmed for this part number per ordering table.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	1.0 V to 5.5 V - enables interoperability with 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters.
Operating Temperature	-40 °C to +125 °C - qualified for under-hood automotive auxiliary modules and industrial motor control environments.
Propagation Delay (t_pd)	13 ns typical at V_CC = 3.3 V, CL = 15 pF - supports reliable operation up to ~70 MHz clock frequency in high-speed control loops.
Input Thresholds	V_IL ≤ 0.3V_CC, V_IH ≥ 0.7V_CC - ensures noise margin >20% of V_CC across full voltage range.
Output Drive Strength	±6 mA at V_CC = 3.0 V, ±12 mA at V_CC = 4.5 V - sufficient to drive 10–15 pF loads directly into standard CMOS/TTL inputs.
Power Dissipation	24 pF CPD - enables accurate dynamic power estimation: P_D = CPD × V_CC² × f_i + Σ(C_L × V_CC² × f_o).

Pinout & Package

TSSOP14 plastic thin shrink small outline package (SOT402-1); 14-lead, 4.4 mm body width, 0.65 mm lead pitch, exposed pad not present.

Pin/Terminal	Circuit Role	Design Meaning
1, 13	nRD (asynchronous reset)	Active-LOW direct reset for Flip-Flop 1 and 2 respectively - forces nQ = H, nQ = L independently of clock.
2, 12	nD (data input)	Primary synchronous data input for each flip-flop - sampled on LOW-to-HIGH clock transition.
3, 11	nCP (clock input)	Positive-edge-triggered clock - initiates sampling of nD only on rising edge meeting setup/hold timing.
4, 10	nSD (asynchronous set)	Active-LOW direct set for Flip-Flop 1 and 2 respectively - forces nQ = L, nQ = H independently of clock.
5, 9	nQ (true output)	Non-inverted registered output - reflects stored nD value after clock edge, unless overridden by nSD/nRD.
6, 8	nQ (complement output)	Inverted registered output - always logic complement of nQ, useful for toggle or differential signaling.
7	GND	Ground reference (0 V) - must be low-impedance connection to minimize switching noise coupling.
14	V_CC	Supply voltage input - decoupling capacitor (100 nF ceramic) required within 5 mm of pin for stable operation.

Key Features

Feature	Design Value
Wide supply voltage range	1.0 V to 5.5 V - eliminates need for separate voltage rails when interfacing mixed-voltage subsystems (e.g., 1.8 V MCU with 3.3 V peripheral bus).
Asynchronous set/reset per channel	Dedicated nSD/nRD pins per flip-flop - enables independent initialization or forced state without disrupting the other channel's operation.
Input clamp diodes	Integrated protection diodes on all inputs - allows safe overvoltage tolerance (up to 7 V) when series resistors limit current to <20 mA.
High ESD robustness	HBM >2000 V, CDM >1000 V - reduces risk of field failure during handling and board assembly in uncontrolled environments.
Industrial temperature grade	-40 °C to +125 °C operation - validated for use in programmable logic controllers, motor drives, and power supply sequencers without derating.

Applications

Industrial PLC Input Latching

Microcontroller GPIO Expansion

Use Scenario: Capturing and holding status of mechanical limit switches in factory automation panels where bounce-free signal conditioning is required.

IC Role / Device Role / Timing Role: Dual D-flip-flop acts as synchronized debouncer and state latch - each channel holds one switch state with independent reset for manual override.

Use Value: Eliminates need for external RC filters or firmware-based debouncing, reducing BOM count and improving deterministic response time (≤13 ns propagation delay).

Use Scenario: Extending limited GPIO count of an ARM Cortex-M0+ MCU in a smart sensor node requiring 4 additional configurable outputs.

IC Role / Device Role / Timing Role: Serves as parallel-output register - MCU writes to shared data bus, then pulses common clock to update both Q outputs simultaneously.

Use Value: Provides two independent, glitch-free outputs with guaranteed setup/hold timing (t_su = 6 ns, t_h = 3 ns at 5 V), enabling precise timing-critical actuation control.

Serial-to-Parallel Data Conversion

State Machine Control Register

Use Scenario: Converting UART RX serial stream into parallel nibble format for LED display driver in a battery-powered metering device.

IC Role / Device Role / Timing Role: Functions as 2-bit shift register stage - cascaded with another 74LV74 to build 4-bit register; clocked by baud-rate-derived timing signal.

Use Value: Supports low-voltage operation down to 1.2 V (V_CC min), enabling direct integration with energy-harvesting power supplies without voltage boosting.

Use Scenario: Storing current state bits in a 4-state traffic light controller implemented with discrete logic instead of FPGA.

IC Role / Device Role / Timing Role: Stores two state variables (e.g., "North-South Green", "East-West Red") - updated synchronously on system clock edge, with asynchronous reset for emergency stop.

Use Value: Asynchronous nRD/nSD enable immediate state reset without waiting for next clock edge - critical for fail-safe transitions in safety-rated lighting systems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC74APWR	Wider industrial temp range (-40 °C to +125 °C), identical pinout, but higher ICC (max 40 μA vs. 20 μA at 5.5 V) and slightly slower t_pd (15 ns typ @ 3.3 V).	Valid for same latching and register roles, but less suitable for ultra-low-power battery applications due to higher static current.	Select when TI ecosystem compatibility or existing LVC-family design reuse is prioritized over minimal quiescent power.
74AUP1G74GW,125	Single-channel, smaller SC-70-6 package, lower V_CC range (0.8–3.6 V), significantly lower power (ICC = 0.9 μA typ), but requires two units for dual functionality.	Applicable only where board space is constrained and dual-channel integration is not mandatory - increases routing complexity and component count.	Choose for space-constrained portable devices operating strictly below 3.6 V, accepting added layout effort for dual-channel implementation.

Compared with SN74LVC74APWR and 74AUP1G74GW,125, the 74LV74PW,112 delivers optimal balance of dual-channel integration, 1.0–5.5 V flexibility, and sub-20 μA quiescent current - making it preferred for mixed-voltage industrial control boards where pin count, voltage adaptability, and power efficiency are jointly critical.

Availability

74LV74PW,112 is available at Aetrix Electronics and suitable for industrial PLC input latching, microcontroller GPIO expansion, serial-to-parallel data conversion, and state machine control register applications requiring stable component supply across extended temperature ranges.

Supply support for 74LV74PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable components including logic ICs, MOSFETs, diodes, and ESD protection devices, with manufacturing rooted in process excellence and automotive-grade quality systems.

The 74LV74 belongs to Nexperia's LV (Low-Voltage) logic family, engineered specifically for robust operation across 1.0–5.5 V supply rails in industrial, computing, and communications equipment where voltage scalability and thermal resilience are essential.

FAQ

What is the maximum clock frequency supported by the 74LV74PW,112?

The 74LV74PW,112 supports up to 110 MHz maximum clock frequency at V_CC = 5.0 V and -40 °C to +85 °C ambient, and 56 MHz at -40 °C to +125 °C. These values derive from measured t_pd (propagation delay) and t_W (minimum pulse width) specifications in Table 7 of the datasheet, with timing validated under load conditions of CL = 15 pF and RL = 1 kΩ.

Can the 74LV74PW,112 operate reliably at 1.2 V supply?

Yes - the 74LV74PW,112 is fully specified down to V_CC = 1.2 V for DC characteristics and functional operation, with propagation delay of 70 ns typical and setup/hold times of 10 ns/–10 ns at that voltage. Static parameters including VIH/VIL thresholds and output drive remain valid, though maximum frequency drops to ~10 MHz at 1.2 V.

Are the set and reset inputs truly asynchronous?

Yes - pins 1/13 (nRD) and 4/10 (nSD) are asynchronous, active-LOW inputs that force immediate state changes regardless of clock activity. When asserted, nRD sets nQ = H and nQ = L; nSD sets nQ = L and nQ = H. These overrides take effect within t_pd (e.g., 14 ns typical at 3.3 V) and are independent of nCP edges or data inputs.

Does the 74LV74PW,112 require external pull-up or pull-down resistors on unused inputs?

No - all inputs have internal clamp diodes and defined logic thresholds, but floating inputs are not recommended. For unused nD, nCP, nSD, or nRD pins, tie to V_CC or GND via 10 kΩ resistor to prevent noise-induced switching and minimize ICC. Unused nQ/nQ outputs may be left open, as they are CMOS totem-pole drivers with no leakage path.

74LV74PW,112 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74LV

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Obsolete

Function:: Set(Preset) and Reset

Type:: D-Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 110 MHz

Max Propagation Delay @ V, Max CL:: 17ns @ 5V, 50pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 12mA, 12mA

Voltage - Supply:: 1V ~ 5.5V

Current - Quiescent (Iq):: 20 µA

Input Capacitance:: 3.5 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

74LV74PW,112 FAQ

1.How can I place an order for 74LV74PW,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LV74PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LV74PW,112 reliable?

The price and inventory of 74LV74PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LV74PW,112 is usually 5 days.

3.What payment methods are accepted for 74LV74PW,112?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LV74PW,112 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74LV74PW,112?

74LV74PW,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LV74PW,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LV74PW,112?

For technical support, including 74LV74PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LV74PW,112 requirements.

6.How does Aetrix verify that 74LV74PW,112 is sourced from the original manufacturer or authorized distributors?

All 74LV74PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LV74PW,112 meets industry standards.

7.What is the process for return or replacement of 74LV74PW,112?

All 74LV74PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LV74PW,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LV74PW,112 part is unused and in its original packaging.

Return procedure for 74LV74PW,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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