NXP Semiconductors 74LVC126AD,112
- Part No.:
- 74LVC126AD,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LVC126AD,112.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 14SO
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVC126AD,112 from Nexperia is a quad 3-state buffer/line driver with 5 V tolerant inputs and outputs, operating from 1.2 V to 3.6 V supply, featuring Schmitt-trigger inputs for noise immunity and IOFF partial power-down protection. It enables level translation between 3.3 V and 5 V logic domains in industrial control backplanes and embedded I/O expansion modules.
For engineers reviewing the 74LVC126AD,112 datasheet, 74LVC126AD,112 pinout, 74LVC126AD,112 application, or 74LVC126AD,112 equivalent, key selection criteria include 5 V tolerance on all I/Os, guaranteed operation down to 1.2 V, -40 °C to +125 °C temperature range, and SO14 (SOT108-1) package compatibility with legacy PCB footprints.
Technical Context
The device implements four independent non-inverting buffers, each with dedicated active-HIGH output enable (nOE) controlling high-impedance state entry/exit. Schmitt-trigger inputs provide hysteresis (typically 0.3 V at VCC = 3.3 V), enabling robust interfacing with slow-rising signals such as mechanical switch debouncing or long-trace sensor lines.
IOFF circuitry actively disables outputs when VCC = 0 V, blocking backflow current up to ±50 mA even with 5.5 V applied to I/O pins - critical for hot-swap and partial-power-down system architectures where subsystems power up/down asynchronously.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.2 V to 3.6 V - supports direct integration into low-voltage microcontroller I/O banks without level shifters |
| Input Voltage Tolerance | Up to 5.5 V - allows safe connection to 5 V legacy peripherals while powered from 1.8 V or 2.5 V rails |
| Propagation Delay | 1.0 ns to 6.0 ns (VCC = 3.0–3.6 V) - ensures timing compliance in 50 MHz digital control loops |
| IOFF Leakage Current | ±10 μA max at VCC = 0 V - prevents bus contention during power sequencing in multi-rail systems |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive ECUs and industrial motor drives |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - meets IEC 61000-4-2 Level 3 for board-level surge resilience |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - sufficient to drive 50 pF loads across 10 cm PCB traces at 25 MHz |
Pinout & Package
74LVC126AD,112 is supplied in SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, JEDEC MS-012 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 (1OE–4OE) | Active-HIGH Output Enable | Individually controls 3-state mode per buffer; LOW disables output, HIGH enables pass-through |
| 2, 5, 9, 12 (1A–4A) | Buffer Input | Schmitt-triggered input accepting 0–5.5 V; immune to noise on long cables or unshielded sensors |
| 3, 6, 8, 11 (1Y–4Y) | Buffer Output | Non-inverting, 3-state output with 5 V tolerance; sinks/sours ±24 mA at 3.0 V |
| 7 | GND | Reference ground for all I/O and internal logic; must be connected to system 0 V plane |
| 14 | VCC | Primary supply rail (1.2–3.6 V); decoupling capacitor (100 nF) required within 5 mm |
Key Features
| Feature | Design Value |
|---|---|
| 5 V tolerant I/O | Enables direct interface with 5 V TTL/CMOS without external level translators in mixed-voltage systems |
| IOFF partial power-down | Prevents damaging back-current flow when VCC is off but I/O lines remain energized at up to 5.5 V |
| Schmitt-trigger inputs | Provides 0.3 V typical hysteresis at 3.3 V, eliminating need for external RC filtering on noisy industrial inputs |
| Wide VCC range (1.2–3.6 V) | Supports battery-powered designs down to single-cell LiFePO₄ (≈2.5 V) and ultra-low-power MCU sleep modes |
| JEDEC-compliant voltage standards | Fully satisfies JESD8-7A (1.65–1.95 V), JESD8-5A (2.3–2.7 V), and JESD8-C/JESD36 (2.7–3.6 V) logic thresholds |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
Use Scenario: Isolating and buffering digital inputs from 24 V field sensors via optocouplers before feeding into 3.3 V microcontroller GPIOs. IC Role / Device Role / Timing Role: Level-translating buffer with Schmitt-trigger noise rejection and 3-state isolation during firmware updates. Use Value: Eliminates external pull-up resistors and RC filters while maintaining signal integrity across 2 m cable runs in EMI-heavy factory environments. | Use Scenario: Driving LED status indicators and relay coils from a 1.8 V automotive MCU while interfacing with 5 V CAN transceiver status lines. IC Role / Device Role / Timing Role: Bidirectional voltage translator and bus isolator during MCU reset sequences. Use Value: Prevents latch-up during cold-cranking (VCC dip to 1.2 V) and avoids bus contention when CAN PHY powers up before MCU. |
| Medical Diagnostic Equipment Backplane | Test & Measurement Instrumentation |
Use Scenario: Routing calibrated analog-to-digital converter (ADC) control signals across isolated power domains in modular patient monitoring units. IC Role / Device Role / Timing Role: Glitch-free signal repeater with IOFF protection during hot-swap of daughter cards. Use Value: Guarantees no transient short-circuit current between isolated 3.3 V ADC domain and 5 V FPGA configuration bus during insertion/removal. | Use Scenario: Synchronizing trigger signals between 5 V legacy oscilloscope front-ends and 2.5 V high-speed digitizer ASICs. IC Role / Device Role / Timing Role: Low-skew (<1.5 ns) buffer with precise enable timing for sub-nanosecond trigger alignment. Use Value: Reduces inter-channel skew to <50 ps over temperature, enabling accurate time-of-flight measurements in ultrasonic NDT systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APWR | TSSOP14 (SOT402-1) package; 0.65 mm pitch; 4.4 mm body width; identical electrical specs | Better thermal performance (7.3 mW/K derating above 81 °C) but requires rework of SO14 footprint | Select when board space is constrained and thermal management priority exceeds legacy footprint compatibility |
| 74LVC126ABQ | DHVQFN14 (SOT762-1) package; 2.5 × 3 mm, 0.5 mm pitch, exposed thermal pad; same logic function | Superior power dissipation (9.6 mW/K derating above 98 °C); no leads reduce parasitic inductance for >100 MHz edge rates | Select for high-density, high-frequency designs where solder-reflow capability and thermal headroom outweigh manual assembly complexity |
Compared with SN74LVC126APWR and 74LVC126ABQ, the 74LVC126AD,112 offers drop-in replacement for legacy SO14 layouts, lower assembly cost in through-hole prototyping, and proven reliability in high-vibration industrial deployments - making it optimal for volume production where footprint continuity and supply chain stability are critical.
Availability
74LVC126AD,112 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, medical diagnostic equipment backplanes, and test & measurement instrumentation requiring stable component supply across extended temperature ranges.
Supply support for 74LVC126AD,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.
The 74LVC126A series belongs to Nexperia's advanced LVC logic family, designed specifically for mixed-voltage system interfacing, partial power-down resilience, and robust operation in harsh industrial and automotive environments.
FAQ
Can 74LVC126AD,112 safely interface a 5 V encoder signal with a 1.8 V microcontroller?
Yes. Its inputs tolerate up to 5.5 V regardless of VCC, and its output VOH/VOL thresholds comply with JESD8-7A at 1.65–1.95 V supply. With VCC = 1.8 V, it delivers VOH ≥ 1.44 V and VOL ≤ 0.45 V driving 4 mA, meeting 1.8 V logic high/low requirements while rejecting encoder EMI via Schmitt-trigger hysteresis.
Does 74LVC126AD,112 require external pull-up resistors on its OE pins?
No. The output enable inputs (1OE–4OE) are CMOS-compatible with rail-to-rail logic thresholds - a direct connection to VCC (for permanent enable) or GND (for permanent disable) suffices. Pull-ups are unnecessary unless implementing open-drain control from another IC, in which case 10 kΩ is typical.
What is the maximum clock frequency supported for clean signal routing?
The device is not a clock buffer but a general-purpose line driver. Its propagation delay (1.0–6.0 ns) and output skew (<1.5 ns) support clean routing of digital control signals up to ≈100 MHz (10 ns period), provided trace lengths are impedance-controlled and load capacitance stays ≤50 pF. For dedicated clock distribution, use a purpose-built clock buffer.
How does IOFF protection behave when VCC is disconnected during system maintenance?
When VCC = 0 V, the IOFF circuit disables all outputs and limits leakage current to ±10 μA maximum, even if 5.5 V is present on any I/O pin. This prevents backfeed into powered-down sections, protecting downstream logic and avoiding false triggering - essential for safe hot-swap of field-replaceable units in telecom and industrial racks.
74LVC126AD,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LVC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 1.2V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74LVC126AD,112 FAQ
1.How can I place an order for 74LVC126AD,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC126AD,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC126AD,112 reliable?
The price and inventory of 74LVC126AD,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC126AD,112 is usually 5 days.
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5.How can I obtain technical support or documentation for 74LVC126AD,112?
For technical support, including 74LVC126AD,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC126AD,112 requirements.
6.How does Aetrix verify that 74LVC126AD,112 is sourced from the original manufacturer or authorized distributors?
All 74LVC126AD,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC126AD,112 meets industry standards.
7.What is the process for return or replacement of 74LVC126AD,112?
All 74LVC126AD,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC126AD,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC126AD,112 part is unused and in its original packaging.
Return procedure for 74LVC126AD,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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