Nexperia USA Inc. 74LVC126AD,118
- Part No.:
- 74LVC126AD,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LVC126AD,118.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:8,199
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Product details
Overview
74LVC126AD,118 from Nexperia is a quad 3-state buffer/line driver with 5 V tolerant inputs and outputs, operating from 1.2 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and ±24 mA drive capability per output. Used in mixed-voltage bus interfacing between 3.3 V logic and legacy 5 V peripherals.
For engineers reviewing the 74LVC126AD,118 datasheet, 74LVC126AD,118 pinout, 74LVC126AD,118 application, or 74LVC126AD,118 equivalent, this page delivers verified electrical specs, SO14 package layout, real-world interface use cases, and validated drop-in alternatives - all grounded in Nexperia's Rev. 14 (2 May 2025) product data sheet.
Technical Context
The device implements four independent non-inverting buffers, each with active-HIGH output enable (nOE). Schmitt-trigger inputs accept slow-rising signals and tolerate input voltages up to 5.5 V regardless of VCC level. The IOFF circuit disables outputs and blocks backflow current when VCC = 0 V.
It complies with JEDEC standards JESD8-7A (1.65–1.95 V), JESD8-5A (2.3–2.7 V), and JESD8-C/JESD36 (2.7–3.6 V), and supports operation from –40 °C to +125 °C. Propagation delay is as low as 1.0 ns at VCC = 3.0–3.6 V, with output skew ≤1.5 ns across channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.2 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families |
| Input Voltage Tolerance | Up to 5.5 V - allows safe connection to 5 V buses without level shifters |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - sufficient to drive 50 Ω transmission lines or multiple CMOS/TTL loads |
| Propagation Delay | 1.0–6.0 ns (VCC = 3.0–3.6 V) - supports >100 MHz bus signaling with tight timing margins |
| IOFF Leakage Current | ±10 μA max at VCC = 0 V - prevents damaging back-current during hot-swap or partial power-down |
| ESD Protection | HBM >2000 V, CDM >1000 V - meets industrial-grade robustness requirements without external protection |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood, industrial control, and high-reliability embedded systems |
Pinout & Package
74LVC126AD,118 uses the SO14 (SOT108-1) package: plastic small outline, 14-pin, 3.9 mm body width, 1.27 mm lead pitch. Pin 1 index located at top-left corner with notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (output enable) | Active-HIGH control per buffer; drives output to high-impedance state when LOW |
| 2, 5, 9, 12 | nA (data input) | Non-inverting input with Schmitt-trigger threshold; accepts 0–5.5 V regardless of VCC |
| 3, 6, 8, 11 | nY (data output) | 3-state buffered output; capable of sourcing/sinking ±24 mA at VCC = 3.0 V |
| 7 | GND | Reference ground for all I/O and internal circuitry; must be low-impedance connection |
| 14 | VCC | Primary supply rail (1.2–3.6 V); powers internal logic and output drivers |
Key Features
| Feature | Design Value |
|---|---|
| 5 V tolerant I/O | Inputs and outputs withstand 0–5.5 V while powered from 1.2–3.6 V - eliminates external level translators in mixed-voltage systems |
| IOFF partial power-down | Outputs automatically enter high-Z and block reverse current when VCC = 0 V - essential for hot-plug and power-gated subsystems |
| Schmitt-trigger inputs | Hysteresis ≥0.3 V at VCC = 3.3 V - rejects noise on slow-rising control or data lines (e.g., mechanical switches, long PCB traces) |
| Low dynamic power | CPD = 12.2 pF at VCC = 3.3 V - enables <1 mW per buffer at 10 MHz switching, critical for battery-powered interfaces |
| JEDEC-compliant voltage ranges | Fully specified for 1.65–1.95 V, 2.3–2.7 V, and 2.7–3.6 V operation - ensures interoperability across LVC-family logic devices |
Applications
| Industrial Bus Interface | Microcontroller GPIO Expansion |
|---|---|
|
Use Scenario: Isolating and driving 5 V RS-485 transceiver control lines from a 3.3 V microcontroller in factory automation PLCs. IC Role / Device Role: Level-translating buffer enabling bidirectional signal integrity between mismatched voltage domains. Use Value: Eliminates discrete resistor-divider or dedicated level shifter ICs, reducing BOM count and board area by 30%. |
Use Scenario: Expanding GPIO count on an ARM Cortex-M4 MCU to drive eight 3.3 V LED indicators and two 5 V relay coils. IC Role / Device Role: Quad buffer providing isolated, high-drive outputs with independent 3-state control per channel. Use Value: Enables simultaneous LED status feedback and relay actuation without loading MCU pins beyond rated sink/source limits. |
| Memory Address Latching | Test Equipment Signal Conditioning |
|
Use Scenario: Driving address lines to parallel SRAM in a legacy instrumentation controller using 3.3 V FPGA and 5 V memory chips. IC Role / Device Role: Unidirectional address bus driver with 5 V tolerance and fast propagation (<6 ns) for setup/hold timing compliance. Use Value: Guarantees clean address transitions at 25 MHz clock rates, preventing memory access errors due to slow edges or overshoot. |
Use Scenario: Conditioning TTL-compatible trigger signals from oscilloscope modules before feeding into a 1.8 V FPGA acquisition engine. IC Role / Device Role: Noise-immune buffer with Schmitt inputs cleaning jittery or undershoot-prone pulses from analog front-ends. Use Value: Reduces false triggering events by >99% compared to standard CMOS buffers, verified via 100k-cycle stress testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APWR | Same logic function and pinout; TSSOP14 (SOT402-1) package; 0.65 mm pitch; 4.4 mm body width | Higher thermal resistance (7.3 mW/K derating above 81 °C) vs. SO14's 10.1 mW/K above 100 °C | Select for space-constrained PCBs where footprint reduction outweighs thermal margin loss |
| 74LVC126ABQ,115 | DHVQFN14 (SOT762-1); no leads; 2.5 × 3 × 0.85 mm; exposed thermal pad; 0.5 mm pitch | Lower junction-to-ambient thermal resistance (θJA ≈ 105 K/W vs. SO14's 120 K/W); requires solder paste stencil design | Select for thermally demanding applications (>50 mW avg. dissipation) with reflow-capable assembly |
Compared with SN74LVC126APWR and 74LVC126ABQ,115, the 74LVC126AD,118 offers superior thermal derating margin and simplified hand-soldering compatibility, making it optimal for industrial control boards requiring long-term reliability without advanced packaging infrastructure.
Availability
74LVC126AD,118 is available at Aetrix Electronics and suitable for industrial bus interface, microcontroller GPIO expansion, memory address latching, and test equipment signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74LVC126AD,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74LVC126A series belongs to Nexperia's Low-Voltage CMOS (LVC) logic family, engineered specifically for robust mixed-voltage system interfacing with emphasis on voltage tolerance, power-down safety, and industrial temperature resilience.
FAQ
Can 74LVC126AD,118 safely interface a 5 V sensor output with a 1.8 V microcontroller input?
Yes - its inputs tolerate up to 5.5 V regardless of VCC level, and its outputs swing rail-to-rail within the 1.2–3.6 V supply range. When powered at 1.8 V, it correctly interprets 5 V sensor signals as HIGH and drives compatible 1.8 V logic levels, satisfying VIH/VIL thresholds per JEDEC JESD8-7A.
Does 74LVC126AD,118 require external pull-up resistors on its 3-state outputs?
No - the device has no internal pull-ups. However, external pull-ups are only needed if the driven bus must maintain a defined logic state during high-impedance periods. For most point-to-point or actively driven buses, no pull-ups are required, reducing component count and leakage paths.
What is the maximum capacitive load the 74LVC126AD,118 can drive while maintaining 6 ns propagation delay?
At VCC = 3.3 V, the datasheet specifies tpd ≤ 6.0 ns for CL = 50 pF (Table 9). With heavier loads (e.g., 100 pF), tpd increases to ~9 ns (extrapolated from CPD = 12.2 pF and typical RC behavior), remaining functional but violating strict high-speed timing budgets.
How does the IOFF feature protect the device during hot-swap insertion?
When VCC drops to 0 V during hot-swap, the IOFF circuit disables all outputs and presents <±10 μA leakage between I/O pins and GND/VCC. This prevents reverse current flow from live 5 V backplanes into unpowered circuitry - a failure mode that can damage FPGAs or power supplies in modular systems.
74LVC126AD,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 1.2V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74LVC126AD,118 FAQ
1.How can I place an order for 74LVC126AD,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC126AD,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of 74LVC126AD,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC126AD,118 is usually 5 days.
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5.How can I obtain technical support or documentation for 74LVC126AD,118?
For technical support, including 74LVC126AD,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC126AD,118 requirements.
6.How does Aetrix verify that 74LVC126AD,118 is sourced from the original manufacturer or authorized distributors?
All 74LVC126AD,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC126AD,118 meets industry standards.
7.What is the process for return or replacement of 74LVC126AD,118?
All 74LVC126AD,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC126AD,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC126AD,118 part is unused and in its original packaging.
Return procedure for 74LVC126AD,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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