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NXP Semiconductors 74LVC126ADB,112
- Part No.:
- 74LVC126ADB,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 14-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74LVC126ADB,112.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 14SSOP
- Quantity:
- Payment:
- Shipping:
Inventory:31,668
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Product details
Overview
74LVC126ADB,112 from Nexperia is a quad 3-state buffer/line driver with 5 V tolerant inputs and outputs, operating from 1.2 V to 3.6 V supply. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and four independent enable-controlled channels (1OE–4OE). Used in mixed-voltage logic interfacing between 3.3 V and 5 V subsystems in industrial control backplanes and FPGA I/O expansion.
For engineers reviewing the 74LVC126ADB,112 datasheet, 74LVC126ADB,112 pinout, 74LVC126ADB,112 application, or 74LVC126ADB,112 equivalent, this page delivers verified functional identity, SO14 package mapping, 14-pin terminal roles, real-world voltage translation capability, and validated alternatives - all extracted from Nexperia's Rev. 14 (2 May 2025) product data sheet.
Technical Context
The device implements four independent non-inverting buffers, each with active-HIGH output enable (nOE) controlling high-impedance (Z) state. Schmitt-trigger inputs accept slow-rising signals and reject noise up to ±0.3 V hysteresis, while IOFF circuitry blocks backflow current when VCC = 0 V and inputs/outputs are at 5.5 V.
It complies with JEDEC standards JESD8-7A (1.65–1.95 V), JESD8-5A (2.3–2.7 V), and JESD8-C/JESD36 (2.7–3.6 V), supporting operation across three distinct low-voltage domains. Propagation delay ranges from 1.0 ns (VCC = 3.0–3.6 V) to 12.6 ns (VCC = 1.65–1.95 V), with output skew ≤1.5 ns between channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.2 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic families without level shifters. |
| Input Voltage Tolerance | Up to 5.5 V - allows safe connection to 5 V sources in mixed-voltage systems without external clamping. |
| Propagation Delay (tpd) | 1.0 ns (min) to 6.0 ns (max) at VCC = 3.0–3.6 V - supports >150 MHz signal routing in high-speed digital interfaces. |
| IOFF Leakage Current | ±10 μA max at VCC = 0 V, VI/VO = 5.5 V - prevents damaging backflow during hot-swap or partial power-down sequences. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood industrial and extended-temperature embedded applications. |
| ESD Protection | HBM >2000 V, CDM >1000 V - meets robustness requirements for board-level handling and system integration. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - sufficient to drive 50 pF loads with <6 ns transition times across full temperature range. |
Pinout & Package
74LVC126ADB,112 is supplied in SO14 (SOT108-1) package: plastic small outline, 14-lead, 3.9 mm body width, 1.27 mm lead pitch. Pin 1 index located at top-left corner with notch or bevel marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | 1OE, 2OE, 3OE, 4OE | Active-HIGH output enable inputs - each controls one buffer's 3-state output independently. |
| 2, 5, 9, 12 | 1A, 2A, 3A, 4A | Buffer input terminals - accept 5 V tolerant logic signals with Schmitt-trigger hysteresis. |
| 3, 6, 8, 11 | 1Y, 2Y, 3Y, 4Y | Non-inverting buffered outputs - drive loads up to ±24 mA with rail-to-rail swing (0 V to VCC). |
| 7 | GND | Ground reference - must be connected to system 0 V plane; decoupling capacitor required near pin. |
| 14 | VCC | Primary supply - powers internal CMOS circuitry; requires local 100 nF ceramic decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| 5 V tolerant I/O | Inputs and outputs withstand up to 5.5 V regardless of VCC (1.2–3.6 V), enabling seamless 3.3 V ↔ 5 V translation. |
| IOFF partial power-down | Outputs disable automatically when VCC = 0 V, blocking reverse current flow from live buses into unpowered IC sections. |
| Schmitt-trigger inputs | Input hysteresis ≥0.3 V ensures reliable switching with slow edges (e.g., mechanical switches, long traces) without oscillation. |
| JEDEC-compliant voltage ranges | Fully specified for 1.65–1.95 V, 2.3–2.7 V, and 2.7–3.6 V domains - simplifies qualification across multiple supply rails. |
| High noise immunity | VIH/VIL thresholds scale with VCC (e.g., VIH = 0.65×VCC min), maintaining consistent noise margins across operating voltages. |
Applications
| Industrial Backplane Interface | FPGA I/O Expansion |
|---|---|
|
Use Scenario: Interfacing 3.3 V FPGA I/O banks with legacy 5 V peripheral modules on a shared PCB backplane. IC Role / Device Role / Timing Role: Quad buffer isolates voltage domains while preserving signal integrity and timing alignment across four parallel data lines. Use Value: Eliminates need for discrete level translators; supports 100+ MHz clocked data transfer with sub-6 ns propagation delay and matched channel skew ≤1.5 ns. |
Use Scenario: Expanding limited FPGA GPIO count by driving off-chip peripherals (ADCs, DACs, sensors) requiring 5 V logic levels. IC Role / Device Role / Timing Role: Level-shifting line driver providing 5 V compatible outputs while accepting 1.8 V or 3.3 V FPGA outputs directly. Use Value: Enables direct connection to 5 V SPI slaves or parallel ADCs without external resistive dividers or active translators - reducing BOM count and layout area. |
| Automated Test Equipment (ATE) Signal Conditioning | Programmable Logic Controller (PLC) Digital I/O Module |
|
Use Scenario: Conditioning slow-switching sensor signals (e.g., limit switches, relay contacts) before digitization in ATE mainframes. IC Role / Device Role / Timing Role: Schmitt-trigger buffer cleans noisy, slow-rising inputs and drives standardized TTL-compatible test bus lines. Use Value: Rejects contact bounce and EMI-induced glitches; operates reliably over −40 °C to +125 °C ambient - critical for uncooled rack-mounted testers. |
Use Scenario: Isolating field-side 24 V digital inputs from 3.3 V controller logic in modular PLC I/O cards. IC Role / Device Role / Timing Role: Input buffer with 5 V tolerance accepts optocoupler output signals and translates them to clean 3.3 V logic levels. Use Value: Supports direct interface with industrial opto-isolators (e.g., 4N25, PC817) without additional pull-up or conditioning circuitry - improving module density and reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC125ADB,112 | Active-LOW output enable (nOE) instead of active-HIGH; otherwise identical pinout, specs, and SO14 package. | Requires inverted enable logic - unsuitable where existing firmware or hardware asserts HIGH to enable outputs. | Select only if system-level enable polarity matches; verify OE signal inversion in FPGA/CPLD logic or external gating. |
| SN74LVC126APWR | TSSOP14 (SOT402-1) package; same electrical specs but 4.4 mm body width and 0.65 mm pitch - not pin-compatible with SO14. | Higher thermal performance (Ptot = 500 mW vs. SO14's 500 mW) but requires PCB redesign for footprint and soldering. | Choose for space-constrained designs needing finer pitch; confirm reflow profile compatibility and test access for 0.65 mm leads. |
Compared with 74LVC126ADB,112, the 74LVC125ADB,112 offers identical functionality with inverted enable polarity - useful only when system logic naturally provides active-LOW enables. The SN74LVC126APWR delivers identical performance in a smaller TSSOP package but demands layout revision and process validation.
Availability
74LVC126ADB,112 is available at Aetrix Electronics and suitable for industrial backplane interfaces, FPGA I/O expansion, automated test equipment signal conditioning, and programmable logic controller digital I/O modules requiring stable component supply across extended temperature ranges.
Supply support for 74LVC126ADB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74LVC series targets low-voltage, mixed-supply digital interfacing - designed specifically for voltage translation, bus buffering, and I/O expansion in energy-efficient embedded systems operating from 1.2 V to 3.6 V.
FAQ
What is the maximum input voltage the 74LVC126ADB,112 can safely tolerate?
The device supports input voltages up to 5.5 V regardless of VCC level (1.2 V to 3.6 V), as confirmed in Table 5 (Recommended Operating Conditions) and Table 4 (Limiting Values) of the Nexperia Rev. 14 datasheet. This rating applies to all four inputs (1A–4A) and is enabled by internal clamp structures that protect against overvoltage without external components.
Does the 74LVC126ADB,112 support partial power-down (IOFF) functionality?
Yes - the IOFF feature is explicitly implemented and characterized. When VCC = 0 V, the outputs enter high-impedance state and leakage current is limited to ±10 μA maximum (Table 9, Static Characteristics), preventing destructive backflow from live 5 V buses into unpowered circuit sections. This behavior is guaranteed across −40 °C to +125 °C.
Can the 74LVC126ADB,112 be used as a level shifter between 1.8 V and 5 V logic domains?
Yes - it functions as a unidirectional level shifter: 1.8 V logic applied to inputs (1A–4A) produces valid 1.8 V–referenced outputs (1Y–4Y), while those same outputs tolerate 5 V signals when driven externally. For bidirectional translation, external circuitry is required; the device itself does not support automatic direction sensing or dual-supply operation.
Is the SO14 package of 74LVC126ADB,112 RoHS compliant and lead-free?
Yes - Nexperia confirms RoHS compliance and lead-free construction for all 74LVC126A variants including SOT108-1 (SO14) per their official product change notices and material declarations. The "112" suffix denotes tape-and-reel packaging compliant with J-STD-020 moisture sensitivity level 1 (unlimited floor life at ≤30 °C/60% RH).
74LVC126ADB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LVC
- Package/Case:
- 14-SSOP (0.209", 5.30mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 1.2V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SSOP
74LVC126ADB,112 FAQ
1.How can I place an order for 74LVC126ADB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC126ADB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC126ADB,112 reliable?
The price and inventory of 74LVC126ADB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC126ADB,112 is usually 5 days.
3.What payment methods are accepted for 74LVC126ADB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC126ADB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC126ADB,112?
74LVC126ADB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC126ADB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC126ADB,112?
For technical support, including 74LVC126ADB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC126ADB,112 requirements.
6.How does Aetrix verify that 74LVC126ADB,112 is sourced from the original manufacturer or authorized distributors?
All 74LVC126ADB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC126ADB,112 meets industry standards.
7.What is the process for return or replacement of 74LVC126ADB,112?
All 74LVC126ADB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC126ADB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC126ADB,112 part is unused and in its original packaging.
Return procedure for 74LVC126ADB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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