NXP Semiconductors 74LVC1G04GN,132
- Part No.:
- 74LVC1G04GN,132
- Manufacturer:
- NXP Semiconductors
- Category:
- Gates and Inverters
- Package:
- 6-XFDFN
- Datasheet:
-
74LVC1G04GN,132.pdf
- Description:
- IC INVERTER 1CH 1-INP 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:190,000
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Product details
Overview
74LVC1G04GN,132 from Nexperia is a single CMOS inverter logic gate with Schmitt-trigger inputs, operating across 1.65 V to 5.5 V supply, supporting mixed-voltage translation between 3.3 V and 5 V systems. It delivers ±24 mA output drive at 3.0 V, features IOFF partial power-down protection, and is qualified for automotive-grade temperature range (–40 °C to +125 °C) in the ultra-compact XSON6 package (0.9 × 1.0 × 0.35 mm). It is used in level-shifting, signal conditioning, and noise-immune digital interface circuits.
For engineers reviewing the 74LVC1G04GN,132 datasheet, 74LVC1G04GN,132 pinout, 74LVC1G04GN,132 application, or 74LVC1G04GN,132 equivalent, this device is selected for low-power, high-noise-immunity inversion in space-constrained industrial control, sensor interface, and portable electronics where voltage translation and IOFF-enabled system power sequencing are required.
Technical Context
The 74LVC1G04GN,132 implements a single unbuffered inverting function with hysteresis on all inputs, enabling robust operation with slow-rising or noisy signals. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V - critical for hot-swap and multi-rail systems.
It complies with JEDEC standards JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), JESD8C (2.7–3.6 V), and JESD36 (4.5–5.5 V), and supports TTL-level input compatibility. Propagation delay ranges from 0.5 ns (VCC = 5.5 V) to 9.5 ns (VCC = 1.65 V, –40 °C to +85 °C), with input capacitance of 5 pF at 3.3 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - enables direct interfacing with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without external level shifters. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - sufficient to drive multiple LVC loads or small capacitive traces without buffering. |
| IOFF Leakage Current | ±2 μA max at VCC = 0 V - ensures safe isolation during partial power-down, preventing bus contention or backfeed damage. |
| Propagation Delay | 0.5 ns (min) to 5.5 ns (max) at VCC = 3.0–3.6 V - supports high-speed signal inversion in timing-critical paths up to ~200 MHz. |
| Input Hysteresis | Typical ΔV = 0.3 V to 0.5 V - rejects noise on slow edges, eliminating false triggering in motor control feedback or sensor signal conditioning. |
| ESD Robustness | HBM > 2000 V, CDM > 1000 V - withstands handling and board-level ESD events without latch-up or parametric shift. |
| Operating Temperature | –40 °C to +125 °C - certified for under-hood automotive, industrial PLC, and outdoor embedded applications. |
Pinout & Package
XSON6 package (SOT1115): extremely thin, leadless, 6-terminal surface-mount package measuring 0.9 mm × 1.0 mm × 0.35 mm with side-wettable flanks omitted - optimized for automated optical inspection and high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (n.c.) | No-connect terminal | Unused pad; must remain unconnected per design - no internal connection or electrical function. |
| 2 (A) | Inverter input | CMOS-compatible digital input with Schmitt-trigger hysteresis; accepts 0–5.5 V regardless of VCC. |
| 3 (GND) | Ground reference | Primary 0 V return path; must be low-impedance and decoupled near the package for noise immunity. |
| 4 (n.c.) | No-connect terminal | Unused pad; electrically isolated - no routing or soldering required. |
| 5 (Y) | Inverter output | Push-pull CMOS output capable of sourcing/sinking ±24 mA; compatible with LVTTL, LVCMOS, and 5 V tolerant loads. |
| 6 (VCC) | Power supply | Single-supply rail (1.65–5.5 V); requires local 100 nF ceramic decoupling capacitor placed ≤2 mm from pin. |
Key Features
| Feature | Design Value |
|---|---|
| Wide supply voltage range | Operates from 1.65 V to 5.5 V - eliminates need for separate voltage translators in mixed-supply systems. |
| Schmitt-trigger inputs | Input hysteresis ≥0.3 V - suppresses chatter on slow or noisy signals (e.g., mechanical switch debouncing, analog comparator outputs). |
| IOFF partial power-down | Output disabled with <±2 μA leakage at VCC = 0 V - prevents back-current flow in powered-down subsystems (e.g., USB suspend, battery-backed modules). |
| Overvoltage-tolerant inputs | Accepts up to 5.5 V regardless of VCC - allows direct connection to 5 V buses while powered from 1.8 V or 3.3 V rails. |
| Low dynamic power | CPD = 14 pF - limits switching power dissipation to <1 μW/MHz at 3.3 V, critical for always-on sensor nodes. |
Applications
| Industrial Sensor Interface | Automotive Body Control Module |
|---|---|
|
Use Scenario: Inverting output of a Hall-effect position sensor before feeding into a microcontroller GPIO with weak internal pull-ups. IC Role / Device Role / Timing Role: Signal polarity correction and noise filtering via Schmitt-trigger input to reject EMI from nearby solenoids or motors. Use Value: Eliminates external RC debounce and discrete transistor inverter, reducing BOM count and PCB area in tight engine bay layouts. |
Use Scenario: Level-shifting wake-up signal from a 5 V CAN transceiver to a 3.3 V microcontroller sleep controller pin. IC Role / Device Role / Timing Role: Voltage translation with IOFF protection - ensures no current flows into the MCU when main VCC is off but CAN bus remains live. Use Value: Enables reliable low-power wake-up without risk of damaging the MCU I/O during battery disconnect or ignition cycling. |
| Portable Medical Device | Smart Home IoT Hub |
|
Use Scenario: Inverting enable signal for a low-noise LDO powering an analog front-end, synchronized with MCU GPIO state. IC Role / Device Role / Timing Role: Logic inversion with precise propagation delay (<5.5 ns) to meet tight power sequencing timing budgets. Use Value: Guarantees clean, glitch-free LDO enable/disable transitions - avoids analog sensor startup errors or ADC offset drift. |
Use Scenario: Driving LED status indicators from a 1.8 V SoC GPIO, requiring higher current and 5 V compatibility for legacy indicator drivers. IC Role / Device Role / Timing Role: Output buffer and voltage translator - provides ±24 mA drive at 3.3 V while accepting 1.8 V logic inputs. Use Value: Replaces dual-stage discrete solutions (MOSFET + resistor), cutting assembly cost and improving reliability in high-volume consumer units. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar single inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G04DBVR | Same logic function and IOFF, but in SOT-23-5 (larger footprint, 2.9 × 1.6 mm) with 5 pins (no n.c. terminals). | Requires more PCB area; lacks the ultra-small XSON6 form factor - unsuitable for wearables or miniaturized modules. | Select when board assembly uses legacy SOT-23 tooling or requires manual rework accessibility. |
| 74LVC1G04GW,125 | Identical electrical specs, but in TSSOP5 (SOT353-1) package: 2.2 mm × 1.35 mm, 5-lead, 0.65 mm pitch - includes exposed thermal pad. | Better thermal performance (Ptot = 250 mW vs. 150 mW for GN), but incompatible with fine-pitch XSON6 placement equipment. | Select for higher ambient temperature environments (>105 °C) or where thermal relief via reflow soldering is prioritized over size. |
Compared with SN74LVC1G04DBVR and 74LVC1G04GW,125, the 74LVC1G04GN,132 offers the smallest footprint and lowest profile (0.35 mm height), making it optimal for ultra-thin devices - though its lower thermal mass limits continuous high-current operation versus the TSSOP5 variant.
Availability
74LVC1G04GN,132 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control modules, and portable medical devices requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC1G04GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET components - spun off from Philips and now part of Beijing JianGuang Asset Management Co., Ltd.
The 74LVC1G04GN,132 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, designed specifically for low-power, mixed-voltage digital interfacing in space- and energy-constrained applications from automotive to IoT edge nodes.
FAQ
Can the 74LVC1G04GN,132 be used with a 1.2 V supply?
No. The absolute minimum supply voltage is 1.65 V per JEDEC JESD8-7 compliance. At 1.2 V, the device will not meet VIH/VIL thresholds, propagation delay, or output drive specifications - operation is undefined and not guaranteed.
Does the IOFF feature work when only GND is connected and VCC is floating?
No. IOFF activation requires VCC = 0 V (actively pulled to ground), not floating. A floating VCC may cause undefined output states or increased leakage; proper power-down sequencing mandates controlled VCC ramp-down to 0 V.
Are the n.c. pins on the SOT1115 package required to be grounded or left open?
Both n.c. pins (1 and 4) are electrically isolated with no internal connection. They must remain unconnected - grounding or routing them risks shorting adjacent terminals due to the 0.4 mm pitch and may compromise solder joint integrity during reflow.
What is the maximum capacitive load the 74LVC1G04GN,132 can drive reliably?
Test data specifies CL = 30–50 pF in dynamic characterization. For reliable signal integrity with <5% overshoot and <1 ns jitter, keep total load (trace + input + probe) ≤50 pF. Exceeding this increases propagation delay and rise/fall time nonlinearly.
74LVC1G04GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LVC
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Inverter
- Number of Circuits:
- 1
- Number of Inputs:
- 1
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 4 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- 0.58V ~ 1.65V
- Input Logic Level - High:
- 1.07V ~ 3.85V
- Max Propagation Delay @ V, Max CL:
- 5ns @ 5V, 50pF
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74LVC1G04GN,132 FAQ
1.How can I place an order for 74LVC1G04GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G04GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G04GN,132 reliable?
The price and inventory of 74LVC1G04GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G04GN,132 is usually 5 days.
3.What payment methods are accepted for 74LVC1G04GN,132?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC1G04GN,132 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC1G04GN,132?
74LVC1G04GN,132 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC1G04GN,132 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC1G04GN,132?
For technical support, including 74LVC1G04GN,132 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G04GN,132 requirements.
6.How does Aetrix verify that 74LVC1G04GN,132 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G04GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G04GN,132 meets industry standards.
7.What is the process for return or replacement of 74LVC1G04GN,132?
All 74LVC1G04GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G04GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G04GN,132 part is unused and in its original packaging.
Return procedure for 74LVC1G04GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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