Nexperia USA Inc. 74LVC1G04GV,125

Overview

74LVC1G04GV,125 from Nexperia is a single CMOS inverter logic gate in SC-74A (SOT753) package with 5 terminals, operating from 1.65 V to 5.5 V supply, featuring ±24 mA output drive at 3.0 V, IOFF partial power-down protection, and Schmitt-trigger input tolerance for slow-edge signals. It enables level translation between 3.3 V and 5 V domains in compact space-constrained digital interfaces.

For engineers reviewing the 74LVC1G04GV,125 datasheet, 74LVC1G04GV,125 pinout, 74LVC1G04GV,125 application, or 74LVC1G04GV,125 equivalent, this device serves as a robust, low-power signal inversion and voltage-level bridging solution in mixed-supply embedded control, sensor interface, and power management subsystems where IOFF-enabled safe power sequencing is required.

Technical Context

This device implements a single unbuffered inverter function with rail-to-rail input voltage tolerance up to 5.5 V independent of VCC, enabling interoperability across 1.65–5.5 V logic families. Its Schmitt-trigger input stage provides hysteresis (typ. 0.3 V at 3.3 V), improving noise immunity against slow-rising/falling signals in noisy industrial environments.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ≤±2 μA and preventing bus contention during hot-swap or partial system power-down. Propagation delay ranges from 0.5 ns (VCC = 5.5 V) to 9.5 ns (VCC = 1.65 V, -40 °C to +85 °C), supporting timing-critical signal conditioning in real-time control loops.

Key Specifications

Pinout & Package

74LVC1G04GV,125 uses the SC-74A (SOT753) surface-mount package: plastic, 5-terminal, no leads, body size 2.7 mm × 1.3 mm × 0.95 mm, with pin 1 located at lower-left corner below marking "V04".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar single inverter applications.

Compared with SN74LVC1G04DBVR and 74AUP1G04GW,125, the 74LVC1G04GV,125 uniquely balances full 1.65–5.5 V operation, ±24 mA drive, and IOFF safety - making it optimal for mixed-voltage industrial control where both voltage translation and robust output loading are required.

Availability

74LVC1G04GV,125 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive power sequencing, IoT edge node reset conditioning, and PLC digital input buffering requiring stable component supply across extended temperature and mixed-voltage environments.

Supply support for 74LVC1G04GV,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.

The 74LVC1G04 belongs to Nexperia's LVC logic family - engineered for low-voltage mixed-signal interfacing with emphasis on IOFF safety, wide supply range, and robust ESD tolerance in space-constrained industrial and automotive systems.

FAQ

Can 74LVC1G04GV,125 safely interface a 5 V sensor output with a 1.8 V MCU input?

Yes. Its inputs tolerate up to 5.5 V regardless of VCC, and its output swings rail-to-rail. With VCC = 1.8 V, the device accepts the 5 V sensor signal directly (no external resistor divider needed), and outputs valid 0 V / 1.8 V logic levels compatible with the MCU. The Schmitt-trigger input further rejects noise on the 5 V line.

Does the IOFF feature require external control or enable signals?

No. IOFF is fully automatic and requires no external configuration. When VCC drops to 0 V (or is unpowered), the internal circuitry detects the condition and disables the output driver, limiting leakage to ≤±2 μA. This occurs passively - no OE pin, no biasing, and no additional components are needed.

What is the maximum capacitive load this device can drive while maintaining specified tpd?

At VCC = 3.3 V and Tamb = 25 °C, the device maintains tpd ≤ 4.2 ns (max) with CL = 50 pF, per Table 8 test conditions. Driving >50 pF increases propagation delay nonlinearly and may cause marginal timing in high-speed paths; for loads >50 pF, verify setup/hold margins in final layout or add a buffer stage.

Is the SC-74A (SOT753) package suitable for reflow soldering in standard lead-free processes?

Yes. The SC-74A package is qualified for JEDEC J-STD-020 moisture sensitivity level 1 (MSL-1), meaning it is unlimited floor life and compatible with standard Pb-free reflow profiles (peak 260 °C). Its 0.65 mm pitch and exposed pad-free construction support reliable automated assembly without tombstoning or voiding concerns.