Nexperia USA Inc. 74LVC1G04GX,125

Overview

74LVC1G04GX,125 from Nexperia is a single CMOS inverter logic gate with Schmitt-trigger inputs, operating across 1.65 V to 5.5 V supply, delivering ±24 mA output drive at 3.0 V, and featuring IOFF partial power-down protection for mixed-voltage bus translation in industrial control and sensor interface circuits.

For engineers reviewing the 74LVC1G04GX,125 datasheet, 74LVC1G04GX,125 pinout, 74LVC1G04GX,125 application, or 74LVC1G04GX,125 equivalent, key selection criteria include its 5-terminal X2SON5 package (SOT1226-3), -40 °C to +125 °C temperature rating, sub-5.5 ns propagation delay at 5 V, overvoltage-tolerant 5.5 V inputs, and IOFF-enabled hot-swap capability in level-shifting designs.

Technical Context

This device implements a single unbuffered inverting function with hysteresis on all inputs, enabling robust noise immunity against slow-rising signals in noisy embedded environments. Its IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V - critical for live-insertion in multi-rail systems.

The logic conforms to JEDEC standards JESD8-7, JESD8-5, JESD8C, and JESD36, supporting interoperability across 1.65–5.5 V domains. Input thresholds scale with VCC (e.g., VIH = 0.7×VCC at 4.5–5.5 V), while output drive strength is specified at multiple load conditions up to 24 mA sink/source.

Key Specifications

Pinout & Package

X2SON5 plastic thermal enhanced extremely thin small outline package (SOT1226-3); 5 terminals; body dimensions 0.8 × 0.8 × 0.32 mm; no leads; side-wettable flanks not present; pin 1 index located on lower left corner below marking code "VC".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar single inverter applications.

Compared with SN74LVC1G04DBVR and 74AUP1G04GW,125, the 74LVC1G04GX,125 uniquely combines 5 V input tolerance, IOFF protection, and ultra-small X2SON5 packaging - making it optimal for space- and safety-critical mixed-voltage industrial and automotive interfaces.

Availability

74LVC1G04GX,125 is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, portable medical device logic, and smart energy metering applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across temperature extremes.

Supply support for 74LVC1G04GX,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for reliability and energy efficiency in industrial, automotive, and consumer markets.

The 74LVC1G04GX,125 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, engineered for robust mixed-voltage interoperability, low dynamic power, and seamless integration into space-constrained, thermally demanding embedded systems.

FAQ

Can 74LVC1G04GX,125 be used as a level shifter between 5 V and 3.3 V logic?

Yes - its inputs tolerate up to 5.5 V regardless of VCC, and it operates down to 1.65 V. When powered at 3.3 V, it accepts 5 V inputs and outputs 0 V/3.3 V levels, enabling unidirectional 5 V → 3.3 V translation without external components. Bidirectional use requires additional circuitry.

What is the maximum capacitive load this inverter can drive reliably?

At VCC = 3.0 V and 24 mA output drive, the device supports ≤50 pF total load capacitance (including PCB trace and input capacitance of downstream devices) while maintaining ≤5.5 ns propagation delay and clean signal edges per datasheet Fig. 5 test conditions.

Does the IOFF feature work when VCC is disconnected but GND remains connected?

Yes - IOFF activates when VCC = 0 V, regardless of GND state. With GND connected and VCC floating or grounded, the output is actively disabled and leakage remains ≤±2 μA, preventing back-current into other powered rails - confirmed in Table 7 and Section 1. General description.

Is the Schmitt-trigger hysteresis value specified in the datasheet?

No - the datasheet specifies Schmitt-trigger action qualitatively and confirms noise immunity, but does not publish explicit hysteresis voltage (ΔV) values. Hysteresis is inherent to the input structure and validated via functional testing per JEDEC JESD78; design margin should assume ≥0.3 V typical based on VIH/VIL spacing at common VCC points.