Nexperia USA Inc. 74LVC1G06GV,125

Overview

74LVC1G06GV,125 from Nexperia is a single CMOS inverter with open-drain output, designed for level translation between 3.3 V and 5 V logic domains. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operates across 1.65 V to 5.5 V supply. Used in I²C bus pull-up interfaces, GPIO signal conditioning, and mixed-voltage sensor interfacing.

For engineers reviewing the 74LVC1G06GV,125 datasheet, 74LVC1G06GV,125 pinout, 74LVC1G06GV,125 application, or 74LVC1G06GV,125 equivalent, key selection factors include open-drain drive strength (±24 mA at 3.0 V), -40 °C to +125 °C operation, IOFF-enabled hot-swap capability, and SC-74A (SOT753) package compatibility with high-density PCB layouts.

Technical Context

This device implements a single inverting logic function with an open-drain output stage, enabling wired-OR configurations and bidirectional bus driving. Its Schmitt-trigger input ensures robust switching with slow-rising signals, while the IOFF circuit isolates I/O pins during power-down to prevent back-current flow.

It complies with JEDEC standards JESD8-7, JESD8-5, JESD8C, and JESD36 across its full 1.65–5.5 V supply range and supports overvoltage-tolerant inputs up to 5.5 V - critical for mixed-supply system interoperability without external clamping diodes.

Key Specifications

Pinout & Package

74LVC1G06GV,125 uses the SC-74A (SOT753) surface-mount package: plastic, 5-lead, body size 1.1 mm × 2.7 mm × 1.3 mm, with gull-wing leads and pin 1 index marked "V06" on top surface.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverter-with-open-drain-output applications.

Compared with 74LVC1G06GW,125, the GV offers superior board-area efficiency in high-density designs; versus SN74LVC1G06DBVR, it delivers certified IOFF behavior essential for fail-safe power sequencing in modular electronics.

Availability

74LVC1G06GV,125 is available at Aetrix Electronics and suitable for industrial sensor interface, I²C bus translation, and hot-swappable module control requiring stable component supply across extended temperature ranges.

Supply support for 74LVC1G06GV,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial and consumer electronics.

The 74LVC1G06 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family - engineered for wide-voltage interoperability, low static/dynamic power, and robust operation in harsh environments.

FAQ

Can 74LVC1G06GV,125 drive a 10 kΩ pull-up to 5 V while powered from 3.3 V?

Yes. With VCC = 3.3 V, the device sinks up to 24 mA at VOL ≤ 0.55 V (per datasheet Table 7). A 10 kΩ pull-up to 5 V draws only 0.5 mA, well within spec. Output voltage under load remains < 0.55 V, ensuring valid LOW logic level for 5 V receivers.

Does the IOFF feature work when VCC is disconnected but GND remains connected?

Yes. IOFF activates when VCC = 0 V, regardless of GND continuity. The datasheet specifies IOFF leakage ≤ ±2 μA with VI or VO = 5.5 V and VCC = 0 V (Table 7), confirming effective isolation during true power-off conditions.

Is the SC-74A (SOT753) package compatible with standard SOT-23 reflow profiles?

Yes. SOT753 shares thermal mass and lead geometry with JEDEC-standard SOT-23-5. Nexperia qualifies it for IPC/JEDEC J-STD-020D reflow profiles, including peak temperatures up to 260 °C - compatible with standard lead-free assembly processes.

What is the maximum capacitive load the output can drive while maintaining tpd ≤ 4 ns at 5 V?

At VCC = 5 V, tpd ≤ 4 ns is guaranteed for CL ≤ 50 pF (Table 10). This includes probe/jig capacitance. For clean signal integrity, keep total load (PCB trace + receiver input + probe) ≤ 45 pF to retain margin against process/voltage/temp variation.