Nexperia USA Inc. 74LVC1G123DC-Q100H

Overview

74LVC1G123DC-Q100 from Nexperia is a single retriggerable monostable multivibrator with Schmitt trigger inputs, designed for precise pulse generation and extension in automotive timing circuits. It operates from 1.65 V to 5.5 V, supports dual-edge triggering (A: negative-edge, B: positive-edge), and delivers programmable output pulse widths via external REXT/CEXT components - e.g., 1.2–1.8 μs with REXT = 10 kΩ & CEXT = 100 pF at 3.0–3.6 V. Used in engine control unit (ECU) watchdog signal conditioning and transmission shift timing synchronization.

For engineers reviewing the 74LVC1G123DC-Q100 datasheet, 74LVC1G123DC-Q100 pinout, 74LVC1G123DC-Q100 application, or 74LVC1G123DC-Q100 equivalent, this page provides verified functional behavior, automotive-grade thermal and ESD specs (-40 °C to +125 °C, AEC-Q100 Grade 1), IOFF power-down protection, and direct reset capability - all critical for safety-relevant timing integrity in vehicle subsystems.

Technical Context

This device implements a CMOS-based retriggerable monostable architecture where output pulse width is determined by external REXT and CEXT values, with real-time extension via repeated A or B edge triggers. Its dual-input triggering logic (A active LOW, B active HIGH) enables flexible event synchronization without external logic.

Schmitt-triggered inputs provide hysteresis (e.g., 40–319 mV at VCC = 3.0–3.6 V), ensuring robust noise immunity against slow-rising signals in noisy automotive environments. The internal CLR-to-input gate connection allows both reset and trigger functionality on the same pin, simplifying system-level pulse termination and restart.

Key Specifications

Pinout & Package

VSSOP8 package (SOT765-1): plastic very thin shrink small outline, 8 leads, body width 2.3 mm, lead pitch 0.5 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Compared with SN74LVC1G123DCKR and MC74VHC1G123DTT1G, the 74LVC1G123DC-Q100 uniquely combines AEC-Q100 Grade 1 qualification, IOFF protection, and ±24 mA drive - making it the sole option for safety-critical, high-temperature automotive timing where power sequencing and noise immunity are non-negotiable.

Availability

74LVC1G123DC-Q100 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, and advanced driver assistance systems requiring stable component supply across automotive production lifecycles.

Supply support for 74LVC1G123DC-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVC1G123-Q100 belongs to Nexperia's automotive-qualified LVC logic family, engineered specifically for robust, low-power timing functions in harsh-temperature vehicle subsystems where reliability and signal integrity are paramount.

FAQ

What is the minimum external capacitor value supported for stable pulse generation?

The datasheet specifies stable operation down to CEXT = 10 pF with REXT = 5 kΩ at VCC ≥ 4.5 V. At lower voltages (e.g., 1.65–1.95 V), minimum recommended CEXT increases to 35 pF to maintain timing accuracy and avoid jitter. Values below these thresholds may cause inconsistent pulse width or failure to trigger.

Can the CLR pin be used simultaneously for reset and trigger functions in the same design?

Yes - CLR performs dual roles: a LOW-going edge forces immediate Q = LOW (reset), while a HIGH-going edge initiates a new monostable pulse. This is enabled by internal gating and does not require external logic. However, simultaneous assertion of A/B and CLR edges must follow setup/hold timing (≥2.5 ns at VCC = 3.3 V) to avoid metastability.

How does the IOFF feature behave during partial power-down of a multi-rail system?

When VCC drops to 0 V while inputs remain biased (e.g., at 3.3 V), the IOFF circuit disables all outputs and isolates internal nodes, limiting leakage to ≤±10 μA. This prevents reverse current flow from powered I/O rails into the unpowered IC, protecting both the device and upstream drivers in complex automotive power architectures.

Is the 74LVC1G123DC-Q100 compatible with 1.8 V logic systems?

Yes - it is fully specified down to VCC = 1.65 V and supports 1.8 V operation with guaranteed VOH ≥ VCC − 0.1 V and VOL ≤ 0.45 V at 4 mA load. Input thresholds scale with VCC (e.g., VT+ = 0.97–1.52 V at 2.3–3.6 V), ensuring reliable detection of 1.8 V logic levels without external level shifters.