Nexperia USA Inc. 74LVC1G123GD,125
- Part No.:
- 74LVC1G123GD,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Multivibrators
- Package:
- 8-XFDFN
- Datasheet:
-
74LVC1G123GD,125.pdf
- Description:
- IC MULTIVIBRATOR 5.3NS 8XSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVC1G123GD,125 from Nexperia is a single retriggerable monostable multivibrator with Schmitt trigger inputs, designed for precise pulse generation and extension in mixed-voltage systems. It supports 1.65 V to 5.5 V supply, delivers ±24 mA output drive at 3.0 V, features IOFF power-down protection, and enables programmable pulse widths via external REXT/CEXT (e.g., 1.2–1.8 μs with 10 kΩ/100 pF). It is used in timing control circuits for industrial sensors and level-shifting interfaces between 3.3 V and 5 V domains.
For engineers reviewing the 74LVC1G123GD,125 datasheet, 74LVC1G123GD,125 pinout, 74LVC1G123GD,125 application, or 74LVC1G123GD,125 equivalent, key selection criteria include retriggerable pulse extension capability, Schmitt-trigger noise immunity, IOFF-enabled partial power-down operation, and compatibility with both 3.3 V and 5 V logic families in mixed-supply designs.
Technical Context
The device implements a dual-edge-triggered monostable architecture: input A responds to negative edges, input B to positive edges, and CLR provides both active-Low reset and positive-edge trigger functionality. Its internal gating allows pulse extension on successive triggers without requiring external logic.
Schmitt-trigger inputs provide hysteresis (e.g., 40–319 mV over 1.65–5.5 V), enabling robust operation with slow-rising signals. The IOFF circuit disables outputs during power-down, preventing backflow current - critical for hot-swap and partial-power-down systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 1.65 V to 5.5 V - supports direct interface with 3.3 V and 5 V logic, eliminating level shifters in mixed-voltage designs. |
| Output drive strength | ±24 mA at VCC = 3.0 V - sufficient to directly drive LEDs, small relays, or fanout to multiple LVC inputs. |
| Pulse width (typ.) | 1.2–1.8 μs with REXT = 10 kΩ, CEXT = 100 pF - enables precise short-duration timing for debouncing or strobe generation. |
| Propagation delay (max) | 5.8 ns at VCC = 4.5–5.5 V, CL = 15 pF - ensures minimal latency in high-speed timing chains. |
| IOFF leakage | ±10 μA at VCC = 0 V - prevents damaging back-current when powered down while other rails remain active. |
| Input hysteresis (VH) | 40–363 mV depending on VCC - rejects noise on slow or noisy control lines (e.g., mechanical switch inputs). |
| Operating temperature | −40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and motor control environments. |
Pinout & Package
XSON8 package (SOT996-2): plastic extremely thin small outline, no leads, 8 terminals, body size 1.2 × 1.0 × 0.35 mm, pin 1 indicator at lower-left corner below marking code Y3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Negative-edge triggered input | Starts or extends output pulse on HIGH-to-LOW transition; enables edge-sensitive triggering from open-drain or push-pull sources. |
| B | Positive-edge triggered input | Starts or extends output pulse on LOW-to-HIGH transition; complements A for flexible trigger source compatibility. |
| CLR | Direct reset / positive-edge trigger | Terminates Q output immediately when pulled LOW; also initiates new pulse on rising edge - dual-function control pin. |
| GND | Ground reference | 0 V return path for all internal logic and output drivers; must be low-impedance for stable timing and noise immunity. |
| Q | Active-HIGH output | Drives HIGH for programmed duration; retains state until reset or retrigger - suitable for enable, strobe, or gate signals. |
| CEXT | External capacitor connection | Connects to timing capacitor; sets base pulse width with REXT/CEXT node - decouples timing accuracy from supply variation. |
| REXT/CEXT | Shared resistor/capacitor node | Completes RC timing network; internal connection allows single external component for basic monostable configuration. |
| VCC | Supply voltage | Power rail for logic and output stages; IOFF activates automatically when VCC = 0 V, isolating Q from backfeed paths. |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable monostable operation | Enables indefinite pulse extension via repeated A/B triggers - eliminates need for external counters or microcontroller intervention in long-delay applications. |
| Schmitt-trigger inputs on all pins | Provides 40–363 mV hysteresis, allowing reliable operation with slow-switching signals (e.g., thermistor-based thresholds or mechanical switches). |
| IOFF partial power-down support | Disables outputs and blocks back-current when VCC = 0 V - essential for PCIe hot-plug, battery-backed subsystems, and modular power sequencing. |
| Wide voltage translation (1.65–5.5 V) | Accepts 5.5 V-tolerant inputs while operating from 1.65 V supply - simplifies interconnection between legacy 5 V peripherals and modern low-voltage controllers. |
| Multiple XSON8 package options | SOT996-2 (1.2 × 1.0 × 0.35 mm) offers ultra-compact footprint for space-constrained PCBs in wearables and IoT edge nodes. |
Applications
| Industrial Sensor Debouncing | Automotive Door Lock Timing |
|---|---|
|
Use Scenario: Mechanical limit switch in factory automation generates contact bounce lasting up to 10 ms. IC Role / Device Role / Timing Role: Monostable configured with REXT = 100 kΩ, CEXT = 100 nF generates clean 10 ms output pulse per valid edge. Use Value: Eliminates false triggers in PLC input modules without software filtering - reduces CPU load and improves real-time response. |
Use Scenario: Door lock actuator requires 500 ms enable pulse after valid key fob signal detection. IC Role / Device Role / Timing Role: Triggered by microcontroller GPIO; pulse extended via B-input retrigger if door position sensor confirms motion. Use Value: Guarantees full actuation time even with variable mechanical response - avoids partial lock engagement and warranty claims. |
| USB Hot-Plug Detection | Motor Start-Up Delay |
|
Use Scenario: USB port detects VBUS presence and must assert "port ready" only after 100 ms stabilization. IC Role / Device Role / Timing Role: CLR driven by VBUS; Q output enables USB transceiver after fixed delay set by REXT/CEXT. Use Value: Meets USB 2.0 enumeration timing requirements without firmware involvement - improves plug-and-play reliability. |
Use Scenario: Conveyor belt motor controller delays start-up for 2 s after safety interlock release. IC Role / Device Role / Timing Role: Retriggerable mode allows pause/resume of delay via emergency stop input on CLR. Use Value: Enables safe restart without resetting entire sequence - reduces downtime in continuous production lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G123DBVR | TSSOP-5 package (5-pin), non-retriggerable, single-shot only; no CLR retrigger function. | Limited to fixed-duration pulses; cannot extend output beyond initial timing period. | Select only when pulse extension is unnecessary and board space permits larger TSSOP-5 footprint. |
| 74LVC2G123DC,125 | Dual-channel version in VSSOP-8; identical electrical specs but doubles channel count. | Reduces component count in multi-signal timing applications (e.g., dual encoder index pulse conditioning). | Choose when two independent monostables are required - avoids routing complexity of two discrete devices. |
Compared with SN74LVC1G123DBVR, the 74LVC1G123GD,125 adds retriggerability and CLR edge-trigger capability, enabling adaptive timing; versus 74LVC2G123DC,125, it saves board area and cost in single-channel use cases where dual functionality is unused.
Availability
74LVC1G123GD,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, automotive body electronics, and USB peripheral timing applications requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for 74LVC1G123GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance logic, analog, and MOSFET solutions, with leadership in automotive-grade reliability and energy-efficient design.
The 74LVC1G123 belongs to Nexperia's LVC logic family, engineered for low-voltage operation (1.65–5.5 V), robust noise immunity, and seamless integration in mixed-supply systems - targeting industrial control, automotive sub-systems, and portable electronics.
FAQ
What is the minimum external capacitor value supported for stable timing?
The datasheet specifies stable operation down to CEXT = 0 pF (no capacitor), where timing defaults to internal propagation delay (~2.5 ns). For programmable pulse widths, CEXT ≥ 10 pF is recommended to ensure predictable RC behavior and minimize sensitivity to stray capacitance in layout.
Can the 74LVC1G123GD,125 operate with VCC = 1.65 V and still drive a 24 mA load?
No. At VCC = 1.65 V, the maximum guaranteed output drive is −4 mA (VOH) and 4 mA (VOL); ±24 mA is specified only at VCC = 3.0 V. Driving heavy loads at minimum supply requires verifying VOL/VOH margins against the connected load's threshold voltages.
How does the CLR pin function as both reset and trigger?
CLR asserts active-LOW reset immediately upon falling edge. When held HIGH, a subsequent rising edge on CLR initiates a new monostable pulse - this dual-mode behavior is implemented via internal gating and requires no external components, simplifying control logic.
Is the 74LVC1G123GD,125 pin-compatible with older SOT23-6 versions of the 74LVC1G123?
No. The 74LVC1G123GD,125 uses an 8-terminal XSON8 (SOT996-2) package, whereas legacy SOT23-6 variants have 6 pins and different pin mapping. Migration requires PCB redesign and verification of timing parameter changes due to package parasitics.
74LVC1G123GD,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Monostable
- Independent Circuits:
- 1
- Schmitt Trigger Input:
- Yes
- Propagation Delay:
- 5.3 ns
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65 V ~ 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (2x3)
74LVC1G123GD,125 FAQ
1.How can I place an order for 74LVC1G123GD,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G123GD,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G123GD,125 reliable?
The price and inventory of 74LVC1G123GD,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G123GD,125 is usually 5 days.
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5.How can I obtain technical support or documentation for 74LVC1G123GD,125?
For technical support, including 74LVC1G123GD,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G123GD,125 requirements.
6.How does Aetrix verify that 74LVC1G123GD,125 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G123GD,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G123GD,125 meets industry standards.
7.What is the process for return or replacement of 74LVC1G123GD,125?
All 74LVC1G123GD,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G123GD,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G123GD,125 part is unused and in its original packaging.
Return procedure for 74LVC1G123GD,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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