NXP Semiconductors 74LVC1G123GM,125

Overview

74LVC1G123GM,125 from Nexperia is a single retriggerable monostable multivibrator with Schmitt trigger inputs, designed for precise pulse generation and timing extension in mixed-voltage systems. It operates from 1.65 V to 5.5 V, delivers ±24 mA output drive at 3.0 V, supports retriggering via A (negative-edge) or B (positive-edge) inputs, and features direct reset via CLR - enabling flexible pulse width control in industrial control logic and power sequencing circuits.

For engineers reviewing the 74LVC1G123GM,125 datasheet, 74LVC1G123GM,125 pinout, 74LVC1G123GM,125 application, or 74LVC1G123GM,125 equivalent, this device offers critical timing flexibility in low-power embedded systems where long, extendable pulses, noise-immune input handling, and IOFF-enabled partial power-down operation are required.

Technical Context

The 74LVC1G123GM,125 implements a CMOS-based retriggerable monostable architecture with dual-trigger inputs (A: active LOW edge; B: active HIGH edge) and a shared CLR pin that serves both as reset (LOW-active) and alternate trigger (HIGH-edge). Its Schmitt-triggered inputs provide hysteresis (e.g., 32–363 mV typical at 5.5 V), ensuring robust operation with slow-rising signals and high noise immunity.

Pulse width is externally programmable via REXT/CEXT (e.g., 1.2–1.8 μs with 10 kΩ/100 pF at 3.3 V), and can be extended indefinitely via retriggering or terminated early by CLR. The IOFF circuit disables outputs during power-down, preventing backflow current - a key requirement for hot-swap and battery-backed subsystems.

Key Specifications

Pinout & Package

XQFN8 package (SOT1116): 1.2 × 1.0 × 0.35 mm, no leads, 8-terminal exposed-pad construction optimized for thermal performance and space-constrained PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Compared with SN74LVC1G123DBVR and 74AUP1G123GW,125, the 74LVC1G123GM,125 uniquely combines XQFN8 miniaturization, full CLR dual-function capability, and sub-2 ns propagation delay - making it optimal for space-limited, noise-prone, and high-reliability timing applications.

Availability

74LVC1G123GM,125 is available at Aetrix Electronics and suitable for industrial control logic, automotive body electronics, and test & measurement equipment requiring stable component supply, extended temperature support, and long-term lifecycle assurance.

Supply support for 74LVC1G123GM,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions - delivering energy-efficient, robust components for automotive, industrial, and consumer markets.

The 74LVC1G123GM,125 belongs to Nexperia's LVC logic family, engineered for low-voltage operation with enhanced noise immunity and power-down safety - specifically targeting timing-critical subsystems in harsh environments.

FAQ

What is the minimum external capacitor value supported by the 74LVC1G123GM,125 for stable timing?

The 74LVC1G123GM,125 supports CEXT down to 10 pF at VCC = 5.0 V, with typical pulse widths ranging from ~20 ns (REXT = 1 kΩ) to ~14 ms (REXT = 5 kΩ). For reliable operation across −40 °C to +125 °C, Nexperia recommends ≥100 pF when using REXT ≤ 10 kΩ to minimize temperature-induced timing drift. The 74LVC1G123GM,125 datasheet specifies CEXT = 0 pF is not allowed - a minimum external capacitor is mandatory for functional timing.

Can the 74LVC1G123GM,125 operate with a 1.8 V supply, and what is its output drive capability at that voltage?

Yes, the 74LVC1G123GM,125 is fully specified from 1.65 V to 5.5 V. At VCC = 1.8 V, it delivers VOH ≥ VCC − 0.1 V (≥1.7 V) with IO = −100 μA, and VOL ≤ 0.1 V with IO = 100 μA. While absolute drive strength is reduced versus 3.3 V operation, the 74LVC1G123GM,125 maintains full logic compatibility and timing integrity - making it suitable for low-power sensor interface stages.

How does the CLR pin function as both a reset and a trigger input in the 74LVC1G123GM,125?

In the 74LVC1G123GM,125, CLR is internally connected to input gating logic such that a LOW level forces Q LOW immediately (reset), while a LOW-to-HIGH transition initiates a new output pulse (trigger). This dual mode eliminates the need for external OR logic when implementing "start on button press, stop on emergency signal" behavior. The 74LVC1G123GM,125's internal architecture ensures no race condition between reset and trigger actions.

Is the 74LVC1G123GM,125 pin-compatible with other 74LVC1G123 variants like the TSSOP8 or XSON8 versions?

No - the 74LVC1G123GM,125 uses the SOT1116 XQFN8 package (1.2 × 1.0 mm), which has a different pinout than TSSOP8 (SOT505-2) and standard XSON8 (SOT833-1). Pin mapping differs: for example, GND is pin 4 in SOT1116 but pin 4 in TSSOP8 is also GND, yet Q is pin 5 in SOT1116 but pin 5 in TSSOP8 is Q - however, physical pad layout, thermal pad presence, and solder mask requirements are incompatible. Board redesign is required for package substitution.

What is the maximum retrigger frequency supported by the 74LVC1G123GM,125 before pulse merging occurs?

The 74LVC1G123GM,125 supports retriggering as fast as every 8 ms (typical trtrig at VCC = 5.0 V, CEXT = 0.01 μF), meaning it can sustain ~125 Hz retrigger rate without pulse merging. With smaller CEXT (e.g., 100 pF), minimum retrigger time drops to ~20 ns - enabling >50 MHz edge-rate handling. Pulse merging only occurs if retrigger edges arrive before internal state stabilization; the 74LVC1G123GM,125's architecture guarantees clean retriggering within datasheet-specified limits.