Texas Instruments 74LVC1G126DCKRE4
- Part No.:
- 74LVC1G126DCKRE4
- Manufacturer:
- Texas Instruments
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74LVC1G126DCKRE4.pdf
- Description:
- IC BUF NON-INVERT 5.5V SC70-5
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVC1G126DCKRE4 from Texas Instruments is a single non-inverting bus buffer gate with 3-state output, designed for level translation and bidirectional bus isolation in low-voltage digital systems. It operates from 1.65V to 5.5V VCC, accepts inputs up to 5.5V, delivers ±24mA drive at 3.3V, achieves 3.7ns max propagation delay, and supports Ioff for live insertion in partial-power-down systems - used in high-speed data acquisition and video infrastructure timing paths.
For engineers reviewing the 74LVC1G126DCKRE4 datasheet, 74LVC1G126DCKRE4 pinout, 74LVC1G126DCKRE4 application, or 74LVC1G126DCKRE4 equivalent, key selection criteria include 3-state enable timing (ten/tdis ≤5.5ns), overvoltage-tolerant inputs (5.5V), Ioff leakage (±10μA), thermal resistance (RθJA = 371°C/W), and SC70-5 package compatibility with space-constrained PCB layouts.
Technical Context
The 74LVC1G126DCKRE4 implements a CMOS-based non-inverting buffer with active-high output-enable control (OE). Its 3-state output architecture enables dynamic bus sharing by driving high, low, or entering high-impedance mode based on OE logic state - critical for multiplexed data paths in SSD controllers and video transcoders.
It features overvoltage-tolerant inputs (VI up to 5.5V independent of VCC), true down-translation capability (e.g., 5V input → 3.3V output), and Ioff protection that disables all outputs when VCC = 0V - ensuring robustness during hot-swap and power sequencing in cable modem termination systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65V to 5.5V - supports mixed-voltage system interfacing (e.g., 1.8V MCU to 3.3V peripheral bus) |
| Max Propagation Delay | 3.7ns at 3.3V, CL = 15pF - enables reliable operation in ≥270MHz data paths (1/tpd) |
| Output Drive | ±24mA at 3.3V - sufficient to drive 50Ω transmission lines or fan-out to 10+ LVC loads |
| Ioff Leakage | ±10μA at 5.5V - prevents back-driving and signal corruption during power-down sequences |
| Input Voltage Tolerance | Up to 5.5V regardless of VCC - allows direct connection to 5V legacy logic without external level shifters |
| ESD Rating | 2000V HBM - meets industrial-grade handling requirements per ANSI/ESDA/JEDEC JS-001 |
| Operating Temp | –40°C to +125°C - qualified for automotive under-hood and military radar environments |
Pinout & Package
74LVC1G126DCKRE4 uses the SC70-5 (DCK) package: 2.0mm × 2.1mm body, 0.65mm pitch, 5-pin surface-mount configuration optimized for high-density routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - GND | Ground reference | Primary return path for all internal logic and output current; must be low-impedance to minimize ground bounce |
| 2 - A | Data input | Non-inverting input accepting 0–5.5V signals; internally terminated with standard CMOS input structure |
| 3 - Y | 3-state output | True-buffered output; drives high/low when OE = high, enters high-Z when OE = low |
| 4 - OE | Output-enable control | Active-high enable; must be held low during power-up to prevent bus contention |
| 5 - VCC | Supply voltage | Power rail for logic core and output drivers; requires local 0.1μF bypass capacitor per TI layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Overvoltage-tolerant inputs | Accepts 5.5V inputs at any VCC (1.65–5.5V), eliminating external level-shifting components in mixed-voltage buses |
| Ioff partial-power-down | Disables all outputs and limits leakage to ±10μA when VCC = 0V - essential for hot-plug and modular backplane designs |
| Low propagation delay | 3.7ns max at 3.3V enables sub-4ns timing margins in DDR clock forwarding and video pixel clock distribution |
| Balanced CMOS 3-state outputs | Sinks and sources ±24mA symmetrically - ensures clean signal edges into 50Ω loads without external termination |
| NanoFree™ packaging | SC70-5 footprint (2.0 × 2.1 mm) reduces board area by >50% vs. SOT-23 while maintaining thermal performance (RθJA = 371°C/W) |
Applications
| Cable Modem Termination | Video Transcoder Interface |
|---|---|
|
Use Scenario: Isolating DOCSIS upstream/downstream data paths between RF front-end and baseband processor. IC Role / Device Role / Timing Role: 3-state bus buffer enabling dynamic channel switching and preventing signal contention during reconfiguration. Use Value: Ioff support allows safe insertion/removal of line cards while main chassis remains powered; 5.5V-tolerant inputs interface directly with legacy analog front-end ICs. |
Use Scenario: Routing uncompressed video pixel data between FPGA-based encoder and multi-format transport stream mux. IC Role / Device Role / Timing Role: Low-skew, non-inverting buffer with fast enable/disable for frame-synchronized bus arbitration. Use Value: 3.7ns tpd ensures <1.5ns skew across parallel data lanes; ±24mA drive sustains signal integrity over 8cm FR4 traces at 1080p60 rates. |
| SSD Controller Bus | Military Radar Signal Path |
|
Use Scenario: Interfacing NVMe controller GPIOs to flash memory die enable/control lines in compact M.2 modules. IC Role / Device Role / Timing Role: Level-translating buffer isolating 1.8V controller logic from 3.3V NAND interface signals. Use Value: Down-translation capability allows 1.8V OE control to manage 3.3V Y output; NanoFree™ SC70-5 fits tight spacing constraints near BGA packages. |
Use Scenario: Conditioning ADC/DAC control signals in phased-array radar beamforming subsystems operating at –40°C to +125°C. IC Role / Device Role / Timing Role: Radiation-tolerant bus driver providing glitch-free enable/disable for high-speed serial link configuration registers. Use Value: 125°C rating and latch-up immunity (>100mA per JESD78 Class II) ensure reliability in sealed, conduction-cooled radar enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DCKRE4 | Inverting logic function (A → Y̅); identical electrical specs, pinout, and package | Requires logic inversion in signal path - unsuitable where polarity must be preserved (e.g., clock forwarding) | Select only when system-level inversion is acceptable or compensated elsewhere in the design |
| 74AUP1G126GW,125 | Lower ICC (0.9μA typical), slower tpd (6.4ns @ 3.3V), same SC70-5 package | Better suited for ultra-low-power sensor hubs; insufficient speed for video or high-speed data acquisition | Prefer for battery-powered edge nodes where <1μA quiescent current outweighs 3.7ns timing advantage |
Compared with SN74LVC1G125DCKRE4, 74LVC1G126DCKRE4 preserves signal polarity critical for clock/data alignment; versus 74AUP1G126GW,125, it delivers 43% faster propagation for real-time video processing at marginally higher static power (10μA vs. 0.9μA).
Availability
74LVC1G126DCKRE4 is available at Aetrix Electronics and suitable for high-speed data acquisition, video broadcasting infrastructure, and military radar signal conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC1G126DCKRE4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of heritage in high-reliability industrial and automotive-grade components.
The SN74LVC1G126 series belongs to TI's LVC (Low-Voltage CMOS) logic family, engineered for voltage translation, bus isolation, and low-power 3-state buffering in space- and power-constrained digital systems.
FAQ
What is the maximum input voltage the 74LVC1G126DCKRE4 can tolerate?
The 74LVC1G126DCKRE4 supports input voltages up to 5.5V regardless of VCC level - a key overvoltage tolerance feature enabling direct interfacing with 5V logic without external level shifters. This specification is validated across the full operating temperature range (–40°C to +125°C) and is explicitly defined in the Absolute Maximum Ratings table of the official TI datasheet SCES224S.
Does the 74LVC1G126DCKRE4 support partial power-down operation?
Yes, the 74LVC1G126DCKRE4 includes Ioff circuitry that disables all outputs and limits leakage current to ±10μA when VCC = 0V - meeting JESD78 Class II latch-up immunity. This allows safe live insertion into powered backplanes and prevents back-driving in partially powered systems, as confirmed in Section 7.3.2 of the TI datasheet.
What is the propagation delay of the 74LVC1G126DCKRE4 at 3.3V supply?
The 74LVC1G126DCKRE4 has a maximum propagation delay (tpd) of 3.7ns at VCC = 3.3V, CL = 15pF, and TA = 25°C - measured from A to Y with OE high. This value is guaranteed across –40°C to +85°C per Table 5.6 in the TI datasheet SCES224S and represents the worst-case timing for timing-critical signal routing.
Is the 74LVC1G126DCKRE4 pin-compatible with other SC70-5 logic buffers?
Yes, the 74LVC1G126DCKRE4 shares identical SC70-5 (DCK) pinout with TI's SN74LVC1G125DCKRE4 and compatible LVC-family variants. Pin 1 = GND, Pin 2 = A, Pin 3 = Y, Pin 4 = OE, Pin 5 = VCC - verified in Figure 4 (DCK PACKAGE TOP VIEW) of the TI datasheet SCES224S.
What thermal resistance does the 74LVC1G126DCKRE4 exhibit in its SC70-5 package?
The 74LVC1G126DCKRE4 in the DCK (SC70-5) package has a junction-to-ambient thermal resistance (RθJA) of 371°C/W, as specified in Section 5.4 of the TI datasheet SCES224S. This value assumes standard JEDEC 2-layer board conditions and informs thermal design for continuous operation at full output drive in enclosed industrial environments.
74LVC1G126DCKRE4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-5
74LVC1G126DCKRE4 FAQ
1.How can I place an order for 74LVC1G126DCKRE4 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G126DCKRE4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G126DCKRE4 reliable?
The price and inventory of 74LVC1G126DCKRE4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G126DCKRE4 is usually 5 days.
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74LVC1G126DCKRE4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC1G126DCKRE4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC1G126DCKRE4?
For technical support, including 74LVC1G126DCKRE4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G126DCKRE4 requirements.
6.How does Aetrix verify that 74LVC1G126DCKRE4 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G126DCKRE4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G126DCKRE4 meets industry standards.
7.What is the process for return or replacement of 74LVC1G126DCKRE4?
All 74LVC1G126DCKRE4 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G126DCKRE4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G126DCKRE4 part is unused and in its original packaging.
Return procedure for 74LVC1G126DCKRE4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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