Nexperia USA Inc. 74LVC1G126GM,115
- Part No.:
- 74LVC1G126GM,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74LVC1G126GM,115.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:384
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Product details
Overview
74LVC1G126GM,115 from Nexperia is a single 3-state bus buffer/line driver with Schmitt-trigger inputs, designed for level translation between 1.65 V–5.5 V logic domains in mixed-voltage systems. It delivers ±24 mA output drive at VCC = 3.0 V, supports IOFF partial power-down protection, and operates across –40 °C to +125 °C. Used in I²C bus isolation, sensor interface signal conditioning, and FPGA I/O expansion.
For engineers reviewing the 74LVC1G126GM,115 datasheet, 74LVC1G126GM,115 pinout, 74LVC1G126GM,115 application, or 74LVC1G126GM,115 equivalent, this page provides verified functional identity, XSON6 package mapping, terminal-level design meaning, thermal derating data, and real-world use-case validation - all extracted from Nexperia's Rev. 18.1 (2024) product data sheet.
Technical Context
This device implements a non-inverting buffer with active-high 3-state enable (OE), enabling bidirectional bus control in compact digital subsystems. Its Schmitt-trigger inputs tolerate slow-rising signals (Δt/ΔV ≤ 20 ns/V at VCC = 1.65 V), eliminating external hysteresis components in noisy industrial sensor interfaces.
The IOFF circuit ensures <1 μA power-off leakage when VCC = 0 V, preventing backflow current during hot-swap or partial system shutdown. Input overvoltage tolerance up to 5.5 V allows safe interfacing with 5 V peripherals while powered from 1.8 V or 3.3 V rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 1.65 V to 5.5 V - enables direct operation from 1.8 V, 2.5 V, 3.3 V, and 5 V rails without level shifters |
| Output drive strength | ±24 mA at VCC = 3.0 V - sufficient to drive 50 pF loads with <6 ns propagation delay in 3.3 V systems |
| Propagation delay (A→Y) | 0.5 ns (min) to 4.5 ns (max) at VCC = 3.0–3.6 V - meets timing budgets for high-speed GPIO expansion in microcontroller peripherals |
| IOFF leakage current | ±2 μA max at VCC = 0 V - guarantees safe hot-plug operation without damaging downstream logic |
| ESD robustness | HBM >2000 V, CDM >1000 V - withstands handling and board-level ESD events in automated assembly environments |
| Operating temperature | –40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and outdoor IoT node applications |
| Input hysteresis | Typical 0.3 V at VCC = 3.3 V - rejects noise on long traces or unshielded sensor lines without external RC filtering |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flanks not present; thermal resistance θJA = 220 K/W (JEDEC standard PCB).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output enable input | Active-high control: drives Y to high-impedance when low; must be pulled high or low via 10 kΩ resistor in static designs |
| 2 (A) | Data input | Non-inverting input with Schmitt-trigger threshold; accepts 0–5.5 V regardless of VCC; immune to ringing on 10 cm PCB traces |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output drivers; requires low-inductance connection to PCB ground plane |
| 4 (Y) | Data output | 3-state buffered output; sinks or sources up to 24 mA; high-impedance state isolates bus segments during arbitration |
| 5 (n.c.) | No-connect terminal | Internally unconnected; must remain floating - no routing, soldering, or grounding permitted |
| 6 (VCC) | Power supply | Primary supply rail; bypass capacitor (100 nF X7R) required within 2 mm of pin for stable 50 MHz switching |
Key Features
| Feature | Design Value |
|---|---|
| Wide supply range | 1.65–5.5 V operation eliminates need for separate voltage translators in multi-rail embedded systems |
| IOFF partial power-down | Enables live insertion into powered backplanes by blocking reverse current flow when VCC = 0 V |
| Schmitt-trigger inputs | Provides 0.3–0.5 V hysteresis margin, allowing reliable operation with slow edges from mechanical switches or analog sensors |
| Overvoltage-tolerant inputs | Accepts 5.5 V inputs while powered from 1.65 V - simplifies interconnection with legacy 5 V controllers |
| Low dynamic power | CPD = 25 pF (enabled), 6 pF (disabled) - reduces switching losses in battery-powered edge nodes |
Applications
| Industrial Sensor Interface | I²C Bus Isolation |
|---|---|
|
Use Scenario: Connecting analog temperature/humidity sensors with slow-rising output signals to a 3.3 V microcontroller ADC input. IC Role / Device Role / Timing Role: Signal conditioner and voltage translator that cleans noisy sensor outputs before digitization. Use Value: Schmitt-trigger input eliminates need for external RC filters; IOFF prevents sensor bias current disruption during MCU sleep mode. |
Use Scenario: Isolating multiple I²C slave devices on shared SDA/SCL lines to prevent address conflicts during firmware updates. IC Role / Device Role / Timing Role: Bidirectional 3-state buffer enabling time-multiplexed access to parallel I²C segments. Use Value: Propagation delay <4.5 ns at 3.3 V preserves I²C Fast-mode Plus (1 MHz) timing margins; ±24 mA drive sustains signal integrity across 20 cm traces. |
| FPGA I/O Expansion | Hot-Swap Peripheral Control |
|
Use Scenario: Extending limited FPGA GPIO count to drive LED arrays, relays, and status indicators in programmable logic controllers. IC Role / Device Role / Timing Role: Level-shifting output buffer translating 1.8 V FPGA I/O to 5 V peripheral logic levels. Use Value: 5.5 V input tolerance allows direct connection to 5 V optocouplers; 125 °C rating supports convection-cooled industrial enclosures. |
Use Scenario: Enabling safe insertion/removal of USB-to-serial adapters or CAN transceivers in powered industrial gateways. IC Role / Device Role / Timing Role: Power-domain isolation gate controlling signal path activation only after VCC stabilization. Use Value: IOFF leakage <2 μA prevents backfeeding into unpowered modules; n.c. pin simplifies PCB layout for zero-risk mechanical alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Active-low OE; identical pinout and electrical specs except enable polarity | Requires inverted control signal from host MCU; unsuitable where OE is hardwired high | Select when existing firmware uses active-low enable logic or pull-up/pull-down constraints favor low-active control |
| 74LVC1G17GW,125 | Non-inverting Schmitt-trigger buffer without 3-state; TSSOP5 package (5-pin) | Lacks bus isolation capability; fixed output drive only - no high-Z state for shared-line arbitration | Choose only for point-to-point signal conditioning where bus contention is impossible and space permits larger TSSOP5 footprint |
Compared with SN74LVC1G125DBVR and 74LVC1G17GW,125, the 74LVC1G126GM,115 uniquely combines active-high 3-state control, XSON6 ultra-compact packaging, and guaranteed 125 °C operation - making it optimal for space-constrained, thermally demanding, and multi-drop digital interfaces.
Availability
74LVC1G126GM,115 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus isolation, and FPGA I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC1G126GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74LVC1G126 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, engineered for robust mixed-voltage interoperability, ultra-low static power, and high-noise immunity in space- and power-constrained embedded systems.
FAQ
Can 74LVC1G126GM,115 operate with VCC = 1.65 V while accepting 5 V inputs?
Yes. The device features overvoltage-tolerant inputs rated to 5.5 V independent of VCC. At VCC = 1.65 V, VIH = 0.65 × VCC ≈ 1.07 V and VIL = 0.35 × VCC ≈ 0.58 V, ensuring reliable recognition of 5 V TTL logic levels without damage or malfunction.
What is the significance of the n.c. pin in the XSON6 package?
Pin 5 is internally unconnected and must remain electrically floating. It is not a thermal pad or ground tie - routing, soldering, or grounding this terminal violates Nexperia's qualification and may cause parametric drift or premature failure due to parasitic coupling.
How does IOFF behavior protect downstream circuitry during power sequencing?
When VCC = 0 V, the IOFF circuit disables both input and output buffers, limiting leakage current to ±2 μA. This prevents backflow current from powered downstream ICs (e.g., 5 V microcontrollers) into the unpowered 74LVC1G126GM,115, avoiding latch-up or unintended logic states during staggered power-up sequences.
Is the XSON6 package compatible with standard reflow profiles for lead-free assembly?
Yes. SOT886 (XSON6) is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 and withstands peak reflow temperatures up to 260 °C. Its 0.5 mm height and exposed copper terminals support full-profile lead-free soldering with standard stencil thicknesses (125 μm) and aperture ratios ≥1.5.
74LVC1G126GM,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74LVC1G126GM,115 FAQ
1.How can I place an order for 74LVC1G126GM,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G126GM,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G126GM,115 reliable?
The price and inventory of 74LVC1G126GM,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G126GM,115 is usually 5 days.
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5.How can I obtain technical support or documentation for 74LVC1G126GM,115?
For technical support, including 74LVC1G126GM,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G126GM,115 requirements.
6.How does Aetrix verify that 74LVC1G126GM,115 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G126GM,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G126GM,115 meets industry standards.
7.What is the process for return or replacement of 74LVC1G126GM,115?
All 74LVC1G126GM,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G126GM,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G126GM,115 part is unused and in its original packaging.
Return procedure for 74LVC1G126GM,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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