Nexperia USA Inc. 74LVC1G126GV-Q100H
- Part No.:
- 74LVC1G126GV-Q100H
- Manufacturer:
- Nexperia USA Inc.
- Package:
- SC-74A, SOT-753
- Datasheet:
-
74LVC1G126GV-Q100H.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SC74A
- Quantity:
- Payment:

- Shipping:

Inventory:1,538
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74LVC1G126GV-Q100 from Nexperia is a single-channel 3-state bus buffer/line driver qualified to AEC-Q100 Grade 1 for automotive use, operating from −40 °C to +125 °C with supply voltage range 1.65 V to 5.5 V, ±24 mA output drive at VCC = 3.0 V, and IOFF partial power-down protection. It serves as a level translator between 3.3 V and 5 V logic domains in body control modules and infotainment interfaces.
For engineers reviewing the 74LVC1G126GV-Q100 datasheet, 74LVC1G126GV-Q100 pinout, 74LVC1G126GV-Q100 application, or 74LVC1G126GV-Q100 equivalent, this device is selected for mixed-voltage signal routing where Schmitt-trigger inputs tolerate slow edges, IOFF prevents backfeed during partial power-down, and automotive-grade reliability is mandatory.
Technical Context
This device implements a non-inverting buffer with active-high 3-state enable (OE), supporting bidirectional voltage translation via overvoltage-tolerant inputs rated to 5.5 V independent of VCC. Its Schmitt-trigger input thresholds provide hysteresis (typically 0.3–0.4 V) to suppress noise on slow-rising signals in automotive harness environments.
The IOFF circuit actively disables output leakage when VCC = 0 V, limiting off-state current to ±2 μA while allowing I/O pins to remain safely connected to live buses. Propagation delay ranges from 0.5 ns (VCC = 5.5 V) to 10.5 ns (VCC = 1.65 V, −40 °C to +85 °C), with enable/disable times under 12 ns across full temperature and voltage range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 1.65 V to 5.5 V - supports direct interface with 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without level shifters |
| Output drive | ±24 mA at VCC = 3.0 V - sufficient to drive 50 Ω transmission lines or multiple CMOS inputs in CAN/LIN subsystems |
| IOFF leakage | ±2 μA at VCC = 0 V - prevents damaging back-current when MCU is powered down but peripheral bus remains live |
| Propagation delay | 0.5 ns to 10.5 ns - enables timing-critical signal buffering in high-speed sensor data paths up to 100 MHz |
| Input voltage tolerance | −0.5 V to 5.5 V - allows safe connection to 5 V sources even when VCC = 1.8 V, eliminating external clamping diodes |
| ESD rating | HBM >2000 V, CDM >1000 V - meets automotive assembly and handling requirements per AEC-Q100 stress tests |
| Operating temperature | −40 °C to +125 °C - qualified for engine bay, powertrain, and ADAS ECU mounting locations |
Pinout & Package
74LVC1G126GV-Q100 uses the SC-74A (SOT753) surface-mount package: 5-terminal plastic package, 3.1 mm × 1.7 mm body, 0.95 mm height, with gull-wing leads and pin 1 indicator below marking "V26".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Output enable input | Active-high control: drives Y to high-impedance when low; enables non-inverting pass-through of A when high |
| 2 (A) | Data input | Schmitt-trigger buffered input tolerant to 5.5 V; accepts TTL/CMOS levels regardless of VCC |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output drivers; must be low-impedance for stable 3-state transitions |
| 4 (Y) | Data output | 3-state CMOS output with ±24 mA drive; floats to high-Z when OE = low, mirrors A when OE = high |
| 5 (VCC) | Supply voltage | Primary power rail (1.65–5.5 V); powers internal logic and output stage; IOFF activates when VCC = 0 V |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for automotive operation from −40 °C to +125 °C with lifetime reliability testing per JEDEC JESD47 |
| IOFF partial power-down | Disables output and limits leakage to ±2 μA when VCC = 0 V, enabling hot-swap and power-gating in modular ECUs |
| Overvoltage-tolerant inputs | Accepts 0–5.5 V signals independent of VCC, enabling direct 5 V microcontroller interfacing without external resistors |
| Schmitt-trigger inputs | Provides 0.3–0.4 V hysteresis to reject noise on long PCB traces or cable harnesses in vehicle networks |
| Wide VCC range (1.65–5.5 V) | Eliminates need for separate voltage translators in multi-rail systems such as instrument clusters with mixed 1.8 V and 5 V peripherals |
Applications
| Body Control Module (BCM) | Infotainment Head Unit |
|---|---|
|
Use Scenario: Isolating LIN bus transceiver I/O from a 3.3 V microcontroller while maintaining compatibility with 12 V vehicle battery fluctuations. IC Role / Device Role / Timing Role: Level-translating buffer enabling bidirectional LIN communication with IOFF protection during MCU sleep mode. Use Value: Prevents backfeed current into powered-down MCU I/O pins during vehicle key-off, extending system standby life by eliminating parasitic drain. |
Use Scenario: Driving RGB LED backlighting control lines from a 1.8 V display controller to 5 V LED driver ICs in a center console display. IC Role / Device Role / Timing Role: Non-inverting 3-state driver providing voltage translation and output isolation during display power sequencing. Use Value: Enables precise timing-controlled enable/disable of backlight segments without risk of latch-up or voltage conflict during power ramp-up. |
| Powertrain Control Unit (PCU) | Advanced Driver Assistance Systems (ADAS) |
|
Use Scenario: Buffering throttle position sensor analog-to-digital converter (ADC) reference clock signals in high-noise engine compartments. IC Role / Device Role / Timing Role: Low-jitter, Schmitt-triggered buffer cleaning noisy clock edges before ADC sampling. Use Value: Reduces clock-induced sampling error by suppressing sub-10 ns noise spikes, improving sensor accuracy by ≥0.5 LSB at 12-bit resolution. |
Use Scenario: Interfacing radar processor GPIOs to 5 V CAN transceivers in front-end collision avoidance modules. IC Role / Device Role / Timing Role: 3-state bus buffer isolating processor I/O during CAN bus arbitration and fault recovery. Use Value: Guarantees clean bus release during error frames by forcing high-Z state within 5.5 ns (VCC = 5.5 V), preventing bus contention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G126DBVR | Industrial grade (−40 °C to +85 °C), no AEC-Q100 qualification, identical pinout and electrical specs | Not suitable for under-hood or safety-critical automotive functions requiring Grade 1 thermal rating | Select only for non-automotive or cabin-only applications where extended temperature is not required |
| 74LVC1G125GV-Q100 | Inverting buffer function (A → NOT Y), otherwise identical AEC-Q100 Grade 1 spec, same package and drive strength | Requires logic inversion in signal path; unsuitable where signal polarity must be preserved (e.g., clock distribution) | Use only when system-level logic design accommodates inversion; verify timing impact of added gate delay |
Compared with SN74LVC1G126DBVR, the 74LVC1G126GV-Q100 adds guaranteed operation to +125 °C and AEC-Q100 validation for engine bay deployment; compared with 74LVC1G125GV-Q100, it preserves signal polarity critical for clock and data strobe integrity in time-sensitive automotive subsystems.
Availability
74LVC1G126GV-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, infotainment head units, and ADAS sensor interface designs requiring stable component supply across extended temperature and automotive lifecycle demands.
Supply support for 74LVC1G126GV-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions optimized for automotive, industrial, and mobile applications.
The 74LVC1G126-Q100 belongs to Nexperia's automotive-qualified LVC logic family, designed specifically for robust signal integrity in harsh-temperature vehicle networks requiring low-power, high-noise-immunity buffering with fail-safe power-down behavior.
FAQ
Does 74LVC1G126GV-Q100 support hot-plug operation with live VCC and floating inputs?
Yes. The device features overvoltage-tolerant inputs (−0.5 V to 5.5 V) and IOFF circuitry that activates when VCC = 0 V, limiting input/output leakage to ±2 μA. This allows safe insertion into a powered system where inputs may be driven before VCC ramps, meeting AEC-Q100 hot-insertion test requirements.
What is the maximum capacitive load the output can drive while maintaining specified tpd?
The datasheet specifies dynamic characteristics with 30–50 pF loads (Table 10). At VCC = 3.3 V and Tamb = 25 °C, propagation delay remains within 4.5 ns up to 50 pF. Driving >50 pF increases tpd linearly and may require series termination to prevent ringing in high-speed traces.
Can OE be left unconnected if always enabled?
No. OE is an active-high CMOS input with ±1 μA leakage (Table 7). Leaving it floating risks undefined output state due to noise coupling. Tie OE directly to VCC via a 10 kΩ pull-up resistor for permanent enable, or use a controlled GPIO for dynamic 3-state control.
How does Schmitt-trigger input improve noise immunity in automotive wiring?
Schmitt-trigger inputs provide 0.3–0.4 V hysteresis (difference between VIH and VIL thresholds), rejecting noise spikes <0.3 V amplitude that would cause false toggling on standard CMOS inputs. This is critical for signals traversing long, unshielded harnesses subject to alternator ripple and ignition noise.
74LVC1G126GV-Q100H Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-74A
74LVC1G126GV-Q100H FAQ
1.How can I place an order for 74LVC1G126GV-Q100H through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G126GV-Q100H on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G126GV-Q100H reliable?
The price and inventory of 74LVC1G126GV-Q100H are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G126GV-Q100H is usually 5 days.
3.What payment methods are accepted for 74LVC1G126GV-Q100H?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC1G126GV-Q100H transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC1G126GV-Q100H?
74LVC1G126GV-Q100H orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC1G126GV-Q100H order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC1G126GV-Q100H?
For technical support, including 74LVC1G126GV-Q100H datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G126GV-Q100H requirements.
6.How does Aetrix verify that 74LVC1G126GV-Q100H is sourced from the original manufacturer or authorized distributors?
All 74LVC1G126GV-Q100H products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G126GV-Q100H meets industry standards.
7.What is the process for return or replacement of 74LVC1G126GV-Q100H?
All 74LVC1G126GV-Q100H units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G126GV-Q100H, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G126GV-Q100H part is unused and in its original packaging.
Return procedure for 74LVC1G126GV-Q100H:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC1G126GV-Q100H Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

