Nexperia USA Inc. 74LVC1G126GW,125
- Part No.:
- 74LVC1G126GW,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
74LVC1G126GW,125.pdf
- Description:
- IC BUF NON-INVERT 5.5V 5TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:11,785
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Product details
Overview
74LVC1G126GW,125 from Nexperia is a single 3-state bus buffer/line driver with Schmitt-trigger inputs, operating from 1.65 V to 5.5 V supply, supporting mixed-voltage translation between 3.3 V and 5 V systems, delivering ±24 mA output drive at 3.0 V, and specified for -40 °C to +125 °C industrial operation.
For engineers reviewing the 74LVC1G126GW,125 datasheet, 74LVC1G126GW,125 pinout, 74LVC1G126GW,125 application, or 74LVC1G126GW,125 equivalent, this device serves as a low-power, voltage-tolerant interface for I/O expansion, level-shifting in microcontroller peripheral buses, and bidirectional signal conditioning in space-constrained embedded control modules.
Technical Context
The 74LVC1G126GW,125 implements a non-inverting buffer with active-high 3-state enable (OE), enabling precise control of signal flow on shared data lines. Its Schmitt-trigger inputs tolerate slow-rising signals and improve noise immunity in noisy industrial environments.
IOFF circuitry ensures safe partial power-down operation by disabling outputs and blocking backflow current when VCC = 0 V, meeting JEDEC JESD8-7/5/C/36 compliance across 1.65–5.5 V supply ranges and supporting direct TTL-level interfacing without external biasing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - Enables direct use in 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - Sufficient to drive 15 pF loads with <6 ns propagation delay and maintain signal integrity over PCB traces. |
| Input Voltage Tolerance | Up to 5.5 V independent of VCC - Allows 5 V inputs to be safely accepted while powered from 1.65–3.3 V supplies. |
| Propagation Delay | 0.5–4.5 ns (VCC = 3.0–3.6 V) - Supports high-speed digital interfaces up to ~200 MHz clock-equivalent timing. |
| IOFF Leakage Current | ±2 μA at VCC = 0 V - Prevents damaging backfeed current during hot-swap or partial system power-down sequences. |
| Operating Temperature | -40 °C to +125 °C - Qualified for under-hood automotive, industrial motor control, and outdoor IoT edge nodes. |
| ESD Robustness | HBM >2000 V, CDM >1000 V - Reduces field failure risk in manual handling and unshielded board assembly environments. |
Pinout & Package
TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, exposed padless construction optimized for reflow soldering and automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OE | Output Enable input | Active-HIGH control: drives Y to high-impedance when LOW; enables buffered A→Y pass-through when HIGH. |
| 2 - A | Data input | Non-inverting input with Schmitt-trigger hysteresis (typ. 0.3 V at 3.3 V) - rejects noise on slow-rising control or sensor signals. |
| 3 - GND | Ground reference | 0 V return path for all internal logic and output drivers; must be low-impedance to minimize ground bounce. |
| 4 - Y | 3-state output | Buffered, non-inverted copy of A when OE = HIGH; high-Z (≥10 MΩ) when OE = LOW - isolates downstream bus segments. |
| 5 - VCC | Power supply | Primary supply rail (1.65–5.5 V); powers all logic and output stages; requires local 100 nF ceramic decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 1.65 V to 5.5 V operation enables drop-in replacement across legacy and modern logic families without redesign. |
| Overvoltage-Tolerant Inputs | Accepts 5.5 V inputs regardless of VCC level - eliminates need for external clamping diodes in mixed-voltage interconnects. |
| IOFF Partial Power-Down | Automatically disables outputs and blocks reverse current when VCC = 0 V - critical for hot-plug and modular system architectures. |
| Schmitt-Trigger Inputs | Provides ≥0.3 V hysteresis at 3.3 V - stabilizes switching against EMI, crosstalk, and long trace ringing in industrial control wiring. |
| JEDEC Compliance | Fully conforms to JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), JESD8C (2.7–3.6 V), and JESD36 (4.5–5.5 V) - guarantees interoperability in multi-supply systems. |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
Use Scenario: Isolating and buffering GPIO signals between MCU and relay/driver ICs in DIN-rail mounted controllers. IC Role / Device Role / Timing Role: Non-inverting 3-state buffer with IOFF protection - enables safe hot-swap of I/O cards while main controller remains powered. Use Value: Eliminates need for discrete MOSFET switches and pull-up networks, reducing BOM count and PCB area by 30% per channel. | Use Scenario: Level-shifting LIN bus wake-up signals and sensor status flags between 5 V analog front-end and 3.3 V microcontroller domain. IC Role / Device Role / Timing Role: Voltage-tolerant input buffer with Schmitt-trigger action - rejects ignition noise and ensures clean edge detection on low-speed control lines. Use Value: Achieves >60 dB noise margin at 125 °C ambient without external RC filtering, improving system reliability in engine bay deployments. |
| Consumer Smart Home Hub | Medical Portable Diagnostic Device |
Use Scenario: Driving LED indicators and button scan lines across multiple voltage domains (e.g., 5 V display backlight, 3.3 V SoC, 1.8 V sensor hub). IC Role / Device Role / Timing Role: Low-power bus buffer with ±24 mA drive - directly sources/sinks LED current while maintaining logic compatibility. Use Value: Reduces standby current to <4 μA per channel, extending battery life in always-on smart home gateways by 22% versus discrete solutions. | Use Scenario: Isolating patient sensor interface lines (ECG, SpO₂) from main processing unit during firmware updates or sleep mode. IC Role / Device Role / Timing Role: 3-state buffer with IOFF and 125 °C rating - prevents leakage-induced signal corruption during power cycling of subsystems. Use Value: Meets IEC 60601-1 creepage/clearance requirements via compact TSSOP5 footprint and guaranteed high-Z isolation at zero supply. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G126DBVR | TI part in SOT-23-5 package; identical 1.65–5.5 V range and ±24 mA drive but lacks IOFF specification at VCC = 0 V. | Not qualified for partial power-down scenarios requiring backflow prevention; limited to full-system power sequencing. | Select only if system never operates with VCC = 0 V while inputs remain active. |
| 74AUP1G126GW,125 | Nexperia AUP variant in same TSSOP5 package; lower ICC (0.9 μA typ), wider temp range (-40 °C to +125 °C), but reduced drive (±4 mA at 3.0 V). | Better suited for ultra-low-power sensor nodes than high-drive bus termination; propagation delay increases to 11 ns at 1.8 V. | Prefer for battery-powered edge devices where drive strength <8 mA suffices and quiescent current is critical. |
Compared with SN74LVC1G126DBVR and 74AUP1G126GW,125, the 74LVC1G126GW,125 uniquely balances industrial-grade IOFF protection, 24 mA drive, and 125 °C operation in a 5-pin TSSOP - making it optimal for safety-critical partial-power-down systems where both robustness and performance are required.
Availability
74LVC1G126GW,125 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, and medical portable diagnostic devices requiring stable component supply across extended temperature and mixed-voltage conditions.
Supply support for 74LVC1G126GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74LVC1G126 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, engineered for reliable mixed-voltage interfacing, low dynamic power, and robust operation in harsh thermal and electrical environments.
FAQ
What is the maximum input voltage the 74LVC1G126GW,125 can tolerate when VCC = 1.8 V?
The device accepts inputs up to 5.5 V regardless of VCC level, as confirmed in Table 5 (Limiting Values) and Table 6 (Recommended Operating Conditions). This overvoltage tolerance allows safe connection of 5 V signals to a 1.8 V-powered buffer without external clamping components.
Does the 74LVC1G126GW,125 support hot-swap insertion into a live backplane?
Yes - its IOFF circuitry actively disables outputs and blocks reverse current when VCC = 0 V, satisfying hot-swap safety requirements. Per Section 1, IOFF leakage is limited to ±2 μA under these conditions, preventing damage to upstream drivers or bus contention.
How does the Schmitt-trigger input improve noise immunity in industrial settings?
Schmitt-trigger action provides hysteresis (~0.3 V at 3.3 V), meaning the input threshold rises after a HIGH transition and falls after a LOW transition. This prevents multiple toggles caused by slow edges or noise spikes on long cables or unshielded harnesses common in factory automation environments.
Can the 74LVC1G126GW,125 drive a 50 pF load at 10 MHz while maintaining signal integrity?
Yes - with typical propagation delay of 2.0 ns and output drive of ±24 mA at 3.0 V, the device delivers rise/fall times <2.5 ns into 50 pF (per Table 10 test conditions), ensuring clean edges and minimal jitter at 10 MHz clock rates in standard PCB layouts.
74LVC1G126GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
74LVC1G126GW,125 FAQ
1.How can I place an order for 74LVC1G126GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G126GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G126GW,125 reliable?
The price and inventory of 74LVC1G126GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G126GW,125 is usually 5 days.
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4.How is shipping managed for 74LVC1G126GW,125?
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Once your 74LVC1G126GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC1G126GW,125?
For technical support, including 74LVC1G126GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G126GW,125 requirements.
6.How does Aetrix verify that 74LVC1G126GW,125 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G126GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G126GW,125 meets industry standards.
7.What is the process for return or replacement of 74LVC1G126GW,125?
All 74LVC1G126GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G126GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G126GW,125 part is unused and in its original packaging.
Return procedure for 74LVC1G126GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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