Nexperia USA Inc. 74LVC1G32GN,132

Overview

74LVC1G32GN,132 from Nexperia is a single 2-input OR gate logic IC in XSON6 package (SOT1115), operating from 1.65 V to 5.5 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and ±24 mA output drive at 3.0 V - used in voltage-level translation between 3.3 V and 5 V subsystems in industrial control I/O interfaces.

For engineers reviewing the 74LVC1G32GN,132 datasheet, 74LVC1G32GN,132 pinout, 74LVC1G32GN,132 application, or 74LVC1G32GN,132 equivalent, this page delivers verified functional identity, validated pin mapping for SOT1115, confirmed dynamic timing (tpd ≤ 6.0 ns at 3.3 V), IOFF-enabled power sequencing behavior, and real-world mixed-voltage interface use cases - all grounded in Nexperia's Rev. 16.1 product data sheet.

Technical Context

This device implements standard positive-logic OR functionality (Y = A + B) with Schmitt-trigger inputs enabling robust operation under slow-rising or noisy signals. Its IOFF circuit actively disables outputs during VCC = 0 V, blocking backflow current in partial power-down systems.

It supports JEDEC-compliant voltage interfaces across three ranges (1.65–1.95 V, 2.3–2.7 V, 2.7–3.6 V, 4.5–5.5 V), maintains TTL compatibility, and achieves HBM ESD rating >2000 V and CDM >1000 V - confirming suitability for board-level signal conditioning in space-constrained embedded nodes.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin no-lead outline, 0.9 × 1.0 × 0.35 mm body, 6 terminals, wettable flank-compatible for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with SN74LVC1G32DBVR, the 74LVC1G32GN,132 offers superior board-area efficiency and thermal performance in XSON6; versus 74AUP1G32GW,125, it provides essential 5 V-tolerant input capability critical for industrial I/O bridging - making it the sole option for mixed-voltage translation tasks.

Availability

74LVC1G32GN,132 is available at Aetrix Electronics and suitable for industrial sensor fusion, power sequencing monitors, USB-C status indication, and PLC digital input conditioning requiring stable component supply across extended temperature and mixed-voltage environments.

Supply support for 74LVC1G32GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions - delivering energy-efficient, application-optimized components for automotive, industrial, and consumer markets.

The 74LVC1G32 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, engineered for robust voltage translation, low-power operation, and seamless integration in space-constrained, multi-rail embedded systems.

FAQ

Can 74LVC1G32GN,132 accept 5 V inputs while powered from 3.3 V?

Yes. Its inputs are overvoltage tolerant up to 5.5 V regardless of VCC level - confirmed in Table 6 (VI input voltage: 0 to 5.5 V) and Section 1. This enables safe interfacing between 5 V legacy peripherals and 3.3 V microcontrollers without external clamping.

Does the n.c. pin on SOT1115 require PCB connection?

No. Pin 5 is internally unconnected per Table 3 and Figure 3 pinning diagram. It may be left floating or tied to GND for mechanical stability - but must never be connected to VCC or driven, as it has no internal function or electrical path.

What is the maximum capacitive load this OR gate can drive reliably?

Per Table 10 test conditions and Figure 5, it is characterized up to 50 pF load capacitance with ≤5.5 ns tpd at VCC = 4.5–5.5 V. Driving >50 pF increases propagation delay nonlinearly and may cause marginal timing - add series resistance if driving long traces or high-C buses.

How does IOFF behave during power-down sequencing?

When VCC drops to 0 V, the IOFF circuit disables the output Y (high-impedance state), limiting leakage to ±2 μA max (Table 7). This prevents reverse current flow from other powered rails through Y, protecting downstream circuitry during staggered power removal.